tag: fill

Process Innovations Enabling Next-Gen SoCs and Memories
By Laura Peters - 20 Feb, 2023 - Comments: 0

Achieving improvements in performance in advanced SoCs and packages — those used in mobile applications, data centers, and AI — will require complex and potentially costly changes in architectures, materials, and core manufacturing processes. Among the options under consideration are new compute architectures, different materials, including thinner barrier layers and those with higher th... » read more

Inside Next-Gen Transistors
By Mark LaPedus - 20 Apr, 2017 - Comments: 0

David Fried, chief technology officer at [getentity id="22210" e_name="Coventor"], sat down with Semiconductor Engineering to discuss the IC industry, China, scaling, transistors and process technology. What follows are excerpts of that conversation. SE: In a recent roundtable discussion you talked about some of the big challenges facing the IC industry. One of your big concerns involves th... » read more

ECO Fill Can Rescue Your SoC Tapeout Schedule
By Vikas Gupta - 16 Feb, 2017 - Comments: 0

By Vikas Gupta and Bhavani Prasad Integrated circuit (IC) design and manufacturing is one of the most challenging engineering industries. As soon as a design engineer gets into “the groove” and feels comfortable taping out in a particular technology node, the next technology node shrink is already there to pose a new and greater set of challenges. While it almost goes without saying that... » read more

A Novel Approach To Dummy Fill For Analog Designs Using Calibre SmartFill
By Mentor, a Siemens Business - 19 Oct, 2016 - Comments: 0

With small geometry silicon processes, additional nonfunctional geometric structures are required to maintain layer planarity during the chemical/mechanical polishing (CMP) phase of processing. The automated layout flows to generate such geometries tend to be designed primarily for large system on chip (SOC) digital designs. When applied to mixed-signal layouts, these flows have been seen to ha... » read more

Déjà Vu For CMP Modeling?
By Jeff Wilson - 17 Sep, 2015 - Comments: 0

One definition of design for manufacturing (DFM) is providing knowledge about the impact of the manufacturing process on a design layout to the designers, so they can use that information to improve the robustness, reliability, or yield of their design before tapeout. Essentially, DFM is about designers taking ownership of the full “lifecycle” of a design, and going beyond the required desi... » read more

The Fill Ecosystem Evolves Again
By Jeff Wilson - 23 Jul, 2015 - Comments: 0

Several years ago, we wrote about the ecosystem of fill, and how 20nm technology required a much tighter relationship between the foundry, designers and EDA vendors. While the players remain the same, there have been some interesting shifts in fill techniques and usage as designers move to even-smaller technologies. What continues with each node is the additional complexity of the design flo... » read more

Fill Database Management Strategies At Advanced Nodes
By Jeff Wilson - 13 Nov, 2014 - Comments: 0

Fill has been around for many nodes, and was originally introduced to improve manufacturing results. The foundries learned that by managing density they were able to reduce wafer thickness variations created during chemical-mechanical polishing (CMP) processes, so they introduced density design rule checks (DRC). To meet these density requirements, designers “filled” open areas of the layou... » read more

A Novel Approach To Dummy Fill For Analog Designs
By Mentor, a Siemens Business - 21 Aug, 2014 - Comments: 0

With small geometry silicon processes, additional nonfunctional geometric structures are required to maintain layer planarity during the chemical/mechanical polishing (CMP) phase of processing. The automated layout flows to generate such geometries tend to be designed primarily for large system on chip (SOC) digital designs. When applied to mixed-signal layouts, these flows have been seen to ha... » read more

SoC Integration Mistakes
By Ed Sperling - 26 Feb, 2014 - Comments: 1

Semiconductor Engineering sat down to discuss integration challenges with Ruggero Castagnetti, distinguished engineer at LSI; Rob Aitken, an ARM fellow; Robert Lefferts, director of engineering in Synopsys’ Solutions Group; Bernard Murphy, chief technology officer at Atrenta; and Luigi Capodieci, R&D fellow at GlobalFoundries. What follows are excerpts of that roundtable discussion. S... » read more

The Upside Of Through-Silicon Vias
By Katherine Derbyshire - 17 Oct, 2013 - Comments: 0

Through-silicon vias (TSVs) for 3D integration are superficially similar to damascene copper interconnects for integrated circuits. Both etch the via, into either silicon or a dielectric, line it with a barrier against copper diffusion, then deposit a seed layer prior to filling the via with copper using some form of aqueous deposition. In both processes, the integrity of the diffusion barrier ... » read more

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