Author's Latest Posts

Manage Scaling Challenges For Silicon Success
By Siemens EDA - 12 Oct, 2021 - Comments: 0

Semiconductor companies are faced with significant challenges related to technology scaling, design scaling, and system scaling. These challenges have a broad impact on design development, manufacturing, and functional operation. This paper discusses the challenges and the specific impact of a Silicon Lifecycle Solutions approach that includes DFT, operations, and Embedded Analytics in enabling... » read more

STMicroelectronics Methodology And Process For Heterogeneous Automotive Package Design
By Siemens EDA - 06 Oct, 2021 - Comments: 0

As a leading supplier of automotive semiconductors, STMicroelectronics must continue to move fast to develop and deliver leading-edge solutions. Employing package design as part of system innovation requires the STMicroelectronics Back-End Manufacturing Technology R&D organization to embrace the key driving forces of product development. In the automotive field, package designers need to... » read more

Automated ESD Protection Verification For 2.5D And 3D ICs
By Siemens EDA - 22 Sep, 2021 - Comments: 0

While automated flows for ESD protection verification are well-established for 2D ICs, 2.5D and 3D designs present new challenges in both ESD circuit design and verification. Advanced automated ESD verification methodology accurately and effectively evaluates ESD protection in 2.5/3D IC designs. Ensuring correct and consistent ESD protection in 2.5/3D ICs raises the reliability and product life... » read more

Shortest Resistance Path Deception In ESD Protection Circuit P2P Debug
By Siemens EDA - 08 Sep, 2021 - Comments: 1

Verifying and fixing ESD protection circuit violations is an essential step in tapeout sign-off flows for today’s IC chip designs. As one of the most commonly used ESD verification flows, the point to point (P2P) flow checks the resistances of ESD discharge paths in layout designs to ensure they are within design thresholds. However, when debugging P2P violations, information such as the shor... » read more

How To Maximize Your Competitiveness In The Semiconductor Industry Using Advanced DFT
By Siemens EDA - 07 Sep, 2021 - Comments: 1

Embarking on advanced SoCs without a smart design-for-test (DFT) strategy can be harmful to your bottom line. Being competitive in today’s semiconductor market means adopting integrated, scalable, and flexible solutions to cut DFT implementation time, test costs, and time-to-market. Tessent DFT technologies, developed in partnership with industry leaders, provide the most advanced DFT and yie... » read more

Consistent Test Reuse Across MIL, SIL, And HIL In A Model-Driven Development Workflow
By Siemens EDA - 01 Sep, 2021 - Comments: 0

This paper presents a standards-based, systematic, and automated generative MDD/XIL workflow that helps automotive developers develop their production ECU V&V suites early during software modeling and re-use them throughout the overall systems engineering project. The test cases developed during design can be re-used through to production ECU testing and ultimately for automated regression V&V ... » read more

Connecting Teams With A Collaboration Hub In The Cloud
By Siemens EDA - 25 Aug, 2021 - Comments: 0

Given the complexities inherent in both next-generation products and the underlying components used, effective collaboration is fundamental to successfully navigating the product creation journey. Teams that are better synchronized and aligned are far more likely to deliver a successful product to market on time and on budget. Explore how the Connect application extends the power of PADS Pro... » read more

2.5D And 3D-IC Latch-Up Prevention
By Siemens EDA - 11 Aug, 2021 - Comments: 0

2.5D/3D ICs have evolved into an innovative solution for many design and integration situations, but they present unique verification obstacles that challenge electronic design automation (EDA) tools originally designed for 2D ICs. Automated solutions are needed not only to reduce verification cycles but also to improve the quality and reliability of package designs. Automated verification o... » read more

Harness System-Level Data To Optimize Many-Core AI And ML Chips
By Siemens EDA - 10 Aug, 2021 - Comments: 0

The novel multicore architectures of SoCs for machine learning (ML) and artificial intelligence (AI) applications are expected to deliver huge improvements in power efficiency. However, chip development teams and the customers for their devices face the growing complexity of hardware-software co-optimization, validation, and debug. In short, these SoCs are increasingly difficult to validate and... » read more

The Evolving Landscape Of SoC Vulnerabilities And Analog Threats
By Siemens EDA - 04 Aug, 2021 - Comments: 0

SoC integrators know that a software-only chip security plan leaves devices open to attack. The more effective way to thwart hackers is to combat both digital and analog threats by incorporating security-focused hardware modules built into the core machine design. This paper describes sources of vulnerabilities to cyber attacks and what infrastructure is needed to secure against them. The So... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy