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Aprisa Place-And-Route For Low-Power SoCs

Addressing power challenges through power reduction and multi-power domain methodology support.

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The Aprisa digital design software helps designers address the many challenges of low-power designs. Aprisa is the most flexible IC place-and-route tool on the market—it accepts all industry-standard power formats, has excellent correlation to third-party signoff tools, and is easy to install, set up, and use. With effective technology and impressive usability, the Aprisa software ensures cost-effective tape-outs for power-sensitive designs. This paper introduces the Aprisa low power solution and innovative low-power methodology to quickly converge on low-power-optimized power, performance, and area.

Low Power Challenges in Place-and-Route
Power, performance, and area (“PPA” for short) is a phrase in the IC design community all commonly uses when describing the three key areas to focus on in optimizing an IC design. Traditionally, performance has been the primary focus, but as designs have moved to smaller, more advanced process nodes, and switching activity has become a dominant component in power consumption, power is often the dominant focus in PPA.

How can strict power targets be achieved without sacrificing performance during the implementation phase of the IC design process? Many challenges of achieving low-power during place-and-route (P&R) relate to how well the P&R software handles multiple power domains and the kinds of optimizations the software performs throughout the flow to achieve low power goals.

The P&R software used in the digital implementation flow must be able to buffer on multiple power domains without errors and perform placement of all power management cells such as level shifters, isolation cells, power switch cells, and retention flip-flops. Power-sensitive designs also require routing secondary power/ground pins and routing to the power grid inside the voltage islands.

This white paper examines how the Siemens Aprisa P&R tool addresses these power challenges in two main ways:

  • Through PowerFirst implementation technology that reduces total power consumption
  • Through multi-power domain methodology support

To read more, click here.



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