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Innovative Integration Solutions For SiP Packages Using Fan-Out Wafer Level eWLB Technology
By STATS ChipPAC - 05 Mar, 2018 - Comments: 0

Fan-Out Wafer Level Packaging (FOWLP) has been established as one of the most versatile packaging technologies in the recent past and already accounts for a market value of over 1 billion USD due to its unique advantages. The technology combines high performance, increased functionality with a high potential for heterogeneous integration and reduced overall form factor as well as cost effective... » read more

Fan-Out Wafer Level eWLB Technology As An Advanced System-in-Package Solution
By STATS ChipPAC - 05 Feb, 2018 - Comments: 0

System-in-Package (SiP) technology continues to be essential for higher integration of functional blocks to meet the ever demanding market needs with respect to smaller form factor, lower cost and time to market. A typical SiP incorporates all or some form of Fan-Out Wafer Level packaging, wire bonding or flip chip that serves a multitude of applications such as optoelectronics, RF, power ampli... » read more

Fan-Out Wafer Level eWLB Technology As An Advanced System-In-Package Solution
By STATS ChipPAC - 08 Jan, 2018 - Comments: 0

System-in-Package (SiP) technology continues to be essential for higher integration of functional blocks to meet the ever demanding market needs with respect to smaller form factor, lower cost and time to market. A typical SiP incorporates all or some form of Fan-Out Wafer Level packaging, wire bonding or flip chip that serves a multitude of applications such as optoelectronics, RF, power ampli... » read more

Reliability Of Embedded Wafer-Level BGA For Automotive Radar Applications
By STATS ChipPAC - 11 Dec, 2017 - Comments: 0

With shrinking of chip sizes, Wafer Level Chip Scale Packaging (WLCSP) becomes an attractive and holistic packaging solutions with various advantages in comparison to conventional packages, such as Ball Grid Array (BGA) with flipchip or wirebonding. With the advancement of various fan-out (FO) WLPs, it has been proven to be a more optimal, low cost, integrated and reliable solution compared to ... » read more

Challenges And Improvement Of Reliability In Advanced Wafer Level Packaging Technology
By STATS ChipPAC - 06 Nov, 2017 - Comments: 0

The number of WLCSP (wafer-level packages) used in semiconductor packaging has experienced significant growth since its introduction in 1998. The growth has been driven primarily by mobile consumer products because of the small form factor and high performance enabled in the package design. And it is also attractive to wearable electronics and IoT products. Although WLCSSP is now a widely ac... » read more

Reliability Of eWLB For Automotive Radar Applications
By STATS ChipPAC - 09 Oct, 2017 - Comments: 0

With shrinking of chip sizes, Wafer Level Chip Scale Packaging (WLCSP) becomes an attractive and holistic packaging solutions with various advantages in comparison to conventional packages, such as Ball Grid Array (BGA) with flipchip or wirebonding. With the advancement of various fan-out (FO) WLPs, it has been proven to be a more optimal, low cost, integrated and reliable solution compared to ... » read more

Advanced Packaging For Automotive Dashboard Application
By STATS ChipPAC - 11 Sep, 2017 - Comments: 0

The current automotive market for the IC (integrated circuit) packaging industry has grown significantly due to the increasing need for automation and higher performance in vehicles. These changes in the automotive market will enable cars to be more reliable and intelligent. To address the increasingly complex demands of the automotive market, the semiconductor packaging industry is shifting it... » read more

Fine-Pitch Copper Pillar With Bond On Lead (BOL).
By STATS ChipPAC - 07 Aug, 2017 - Comments: 0

Fine pitch copper (Cu) pillar bump adoption has been growing in high-performance and low-cost flip chip packages. Higher input/output (I/O) density and very fine pitch requirements are driving very small feature sizes such as small bump on a narrow pad or bond-on-lead (BOL) interconnection, while higher performance requirements are driving increased current densities. Assembling such packages u... » read more

28nm Chip-Package Interactions In Large eWLB FO-WLP
By STATS ChipPAC - 10 Jul, 2017 - Comments: 0

To meet the continued demand for form factor reduction and functional integration of electronic devices, Wafer Level Packaging (WLP) is an attractive packaging solution with many advantages in comparison with standard Ball Grid Array (BGA) packages. The advancement of fan-out WLP has made it a more promising solution as compared with fan-in WLP, because it can offer greater flexibility in enabl... » read more

Board Level Reliability Improvement In eWLB
By STATS ChipPAC - 05 Jun, 2017 - Comments: 0

When it comes to reducing form-factor and increasing functional integration of mobile devices, Wafer Level Packaging (WLP) is an attractive packaging solution with many advantages in comparison to standard Ball Grid Array (BGA) packages. With the advancement of various fan-out WLP (FOWLP), it is a more optimal and promising solution compared to fan-in WLP because it can offer greater flexibilit... » read more

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