Author's Latest Posts

Software Due Diligence: A Buyer’s Checklist And Guidelines
By Synopsys - 02 Dec, 2020 - Comments: 0

The potential risk and exposure posed by M&A transactions demand thorough and robust due diligence practices. When an acquisition involves software, it's critical to ensure that associated risks are identified and fully understood. Knowing what questions to ask when performing due diligence is key to avoiding potential risks and legal complications. This is especially true for the acquisiti... » read more

The Growing Market For Specialized Artificial Intelligence IP In SoCs
By Synopsys - 23 Nov, 2020 - Comments: 0

Over the past decade, designers have developed silicon technologies that run advanced deep learning mathematics fast enough to explore and implement artificial intelligence (AI) applications such as object identification, voice and facial recognition, and more. Machine vision applications, which are now often more accurate than a human, are one of the key functions driving new system-on-chip (S... » read more

Lower Process Nodes Drive Timing Signoff Software Evolution
By Synopsys - 10 Nov, 2020 - Comments: 0

A dramatic rise in design complexity has led to a slew of new signoff challenges that impact the ability to predictably meet PPA targets. Smaller technology nodes and larger design sizes have caused the number of corners and modes to grow exponentially leading to much longer turnaround times for timing signoff. Moreover, larger design sizes demand huge compute resources for timing signoff. I... » read more

Comprehensive Simulation Of Power Electronics Systems
By Synopsys - 09 Nov, 2020 - Comments: 0

Power electronics systems are at the heart of many important and growing industries, from all-electric vehicles to renewable energy generation. Optimizing the design of these systems requires accurate modeling and simulation long before construction of physical prototypes. SPICE-level simulation has been the traditional solution and, while it still plays a key role, it cannot satisfy all requir... » read more

Know Your Code: Open Source Security Risks During Development
By Synopsys - 04 Nov, 2020 - Comments: 0

Exploits of software security vulnerabilities can result in loss of sensitive customer and company information, disruption of business operations, and costly litigation. Organizations are increasingly turning to open source software to save time and money, but few have sufficient visibility into, or control of, open source usage to head off potential open source risks. Read this white paper ... » read more

Lower Process Nodes Drive Timing Signoff Software Evolution
By Synopsys - 28 Oct, 2020 - Comments: 0

A dramatic rise in design complexity has led to a slew of new signoff challenges that impact the ability to predictably meet PPA targets. Smaller technology nodes and larger design sizes have caused the number of corners and modes to grow exponentially leading to much longer turnaround times for timing signoff. Moreover, larger design sizes demand huge compute resources for timing signoff. I... » read more

Build Security Into Your SDLC With Coverity
By Synopsys - 07 Oct, 2020 - Comments: 0

Are your developers getting discouraged by too many false positives from security tools that slow them down? You need a solution that boosts their productivity, finds real vulnerabilities, and provides expert remediation guidance. Coverity will help you achieve this and more. Learn about Coverity’s unique technical capabilities and why it should be your go-to solution for static analysis secu... » read more

Monte Carlo Analysis Using Synopsys Custom Design Platform
By Synopsys - 23 Sep, 2020 - Comments: 0

In this 5th video of the series, Kai Wang, Director of Engineering at Synopsys, explains the need of Monte Carlo to improve yield, and how designers use advanced features like variation scoping and sigma amplification to avoid costly MC simulations. Click here to watch this video white paper. » read more

Early Verification Of Multi-Cycle Paths And False Paths In Simulation
By Synopsys - 09 Sep, 2020 - Comments: 0

Timing closure is a critical step in the chip development process. The performance and timing of a design must be verified, and any violations must be investigated and resolved. This includes the specification and verification of timing exceptions. This white paper focuses on false paths and multi-cycle paths, the use of Synopsys Design Constraints (SDC) to specify these exceptions, and the “... » read more

Importance of Dependent Failure Analysis For Safety-Critical IP And SoCs
By Synopsys - 02 Sep, 2020 - Comments: 0

This white paper explains the importance of implementing DFA in the automotive IP and SoC development cycle and how DFA helps meet the technical independence essentials according to the design’s safety requirements. To read more, click here. » read more

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