How to catch many classes of errors “on the fly” when coding register-transfer level (RTL) design and developing the hardware verification language (HVL) testbench.
Two things are certain in chip verification: as many bugs as possible must be found and fixed before fabrication, and this must happen as early as possible in the development process. The much-desired “shift left” in verification requires that advanced analysis and debug technologies be available to engineers from the earliest stages of the project. It is preferable that many classes of errors be detected “on the fly” as the designers code their register-transfer level (RTL) design and the verification team develops the hardware verification language (HVL) testbench and supporting environment. Ideally, the engineers receive suggestions on how to fix these errors interactively as they type in their code.
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