Author's Latest Posts


Using Deep Learning to Secure The CAN Bus From Advanced Intrusion Attacks


A technical paper titled “CANShield: Deep Learning-Based Intrusion Detection Framework for Controller Area Networks at the Signal-Level” was published by researchers at Virginia Tech and others. "As modern vehicles become more connected to external networks, the attack surface of the CAN bus system grows drastically. To secure the CAN bus from advanced intrusion attacks, we propose a sig... » read more

VCMA-Controlled MTJ Devices For Probabilistic Computing Applications


A technical paper titled “Probabilistic computing with voltage-controlled dynamics in magnetic tunnel junctions” was published by researchers at Northwestern University, University of Messina, Western Digital Corporation, and Universitat Jaume I. Abstract: "Probabilistic (p-) computing is a physics-based approach to addressing computational problems which are difficult to solve by convent... » read more

Noise Parameter Survey Of Millimeter Wave GaN HEMT Technologies


A technical paper titled “A Survey of GaN HEMT Technologies for Millimeter-Wave Low Noise Applications” was published by researchers at Wright-Patterson AFB, Teledyne Scientific, HRL Laboratories, BAE Systems, Pseudolithic, Northrop Grumman Corporation, and University of California Santa Barbara. "This article presents a set of measured benchmarks for the noise and gain performance of si... » read more

New Type Of Hardware Trojans Based On Logic Locking


A technical paper titled “Logic Locking based Trojans: A Friend Turns Foe” was published by researchers at University of Maryland and University of Florida. Abstract: "Logic locking and hardware Trojans are two fields in hardware security that have been mostly developed independently from each other. In this paper, we identify the relationship between these two fields. We find that a com... » read more

LLM-Aided AI Accelerator Design Automation (Georgia Tech)


A technical paper titled “GPT4AIGChip: Towards Next-Generation AI Accelerator Design Automation via Large Language Models” was published by researchers at Georgia Institute of Technology. Abstract: "The remarkable capabilities and intricate nature of Artificial Intelligence (AI) have dramatically escalated the imperative for specialized AI accelerators. Nonetheless, designing these accele... » read more

LLM-Assisted Generation Of Formal Verification Testbenches: RTL to SVA (Princeton)


A technical paper titled “From RTL to SVA: LLM-assisted generation of Formal Verification Testbenches” was published by researchers at Princeton University. Abstract: "Formal property verification (FPV) has existed for decades and has been shown to be effective at finding intricate RTL bugs. However, formal properties, such as those written as System Verilog Assertions (SVA), are time-con... » read more

Neuromorphic Hardware Accelerator For Heterogeneous Many-Accelerator SoCs


A technical paper titled “SpikeHard: Efficiency-Driven Neuromorphic Hardware for Heterogeneous Systems-on-Chip” was published by researchers at Columbia University. Abstract: "Neuromorphic computing is an emerging field with the potential to offer performance and energy-efficiency gains over traditional machine learning approaches. Most neuromorphic hardware, however, has been designed wi... » read more

Integration Of Layered Semimetals With Conventional CMOS Platform


A technical paper titled “Layered semimetal electrodes for future heterogeneous electronics” was published by researchers at IIT Madras and Indian Institute of Science Education and Research. Abstract: "Integration of the emerging layered materials with the existing CMOS platform is a promising solution to enhance the performance and functionalities of the future CMOS based integrated cir... » read more

Friction Between Single Layer Graphene And An Atomic Force Microscope Tip


A technical paper titled “Dynamically tuning friction at the graphene interface using the field effect” was published by researchers at University of Illinois Urbana-Champaign and University of California Irvine. Abstract: "Dynamically controlling friction in micro- and nanoscale devices is possible using applied electrical bias between contacting surfaces, but this can also induce unwant... » read more

SRAM-Based IMC For Cryogenic CMOS Using Commercial 5 nm FinFETs


A technical paper titled “Cryogenic In-Memory Computing for Quantum Processors Using Commercial 5-nm FinFETs” was published by researchers at University of Stuttgart, Indian Institute of Technology Kanpur, University of California Berkeley, and Technical University of Munich. Abstract: "Cryogenic CMOS circuits that efficiently connect the classical domain with the quantum world are the co... » read more

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