Author's Latest Posts

Impact of Clustering Methods On Partitioning Decisions For 3DICs (imec, Université libre de Bruxelles)
By Technical Paper Link - 28 Jul, 2023 - Comments: 0

A technical paper titled “Impact of gate-level clustering on automated system partitioning of 3D-ICs” was published by researchers at Université libre de Bruxelles and imec. Abstract: "When partitioning gate-level netlists using graphs, it is beneficial to cluster gates to reduce the order of the graph and preserve some characteristics of the circuit that the partitioning might degrade. ... » read more

Automotive Lidar: Softening The Trade-off Between Ambiguity Range And Speed 
By Technical Paper Link - 28 Jul, 2023 - Comments: 0

A technical paper titled “Overcoming the limitations of 3D sensors with wide field of view metasurface-enhanced scanning lidar” was published by researchers at Université Côte d’Azur and CRHEA. Abstract: "Lidar, a technology at the heart of autonomous driving and robotic mobility, performs 3D imaging of a complex scene by measuring the time of flight of returning light p... » read more

III–V Laser Grown on a Patterned Si Photonics Platform With Light Coupling Into Passive SiN Waveguides
By Technical Paper Link - 28 Jul, 2023 - Comments: 0

A technical paper titled “Unlocking the monolithic integration scenario: optical coupling between GaSb diode lasers epitaxially grown on patterned Si substrates and passive SiN waveguides” was published by researchers at University of Montpellier, Tyndall National Institute, Munster Technological University and Polytechnic University of Bari. Abstract: "Silicon (Si) photonics has recently... » read more

Heat-Tolerant CNT-Based PUFs
By Technical Paper Link - 28 Jul, 2023 - Comments: 0

A technical paper titled “CNT-PUFs: Highly Robust and Heat-Tolerant Carbon-Nanotube-Based Physical Unclonable Functions for Stable Key Generation” was published by researchers at Chemnitz University of Technology, University of Passau, Technical University of Darmstadt, and Fraunhofer Institute for Electronic Nano Systems (ENAS). Abstract: "In this work, we explore a highly robust and... » read more

Direct Synthesis of Planar (2D) Micro and Nanopatterned Epitaxial Graphene on SiC
By Technical Paper Link - 28 Jul, 2023 - Comments: 0

A technical paper titled “Direct synthesis of nanopatterned epitaxial graphene on silicon carbide” was published by researchers at University of Technology Sydney, Ludwig-Maxilimians Universität München, Monash University, and Imperial College London. Abstract: "This article introduces a straightforward approach for the direct synthesis of transfer-free, nanopatterned epitaxial graphene... » read more

Implementing Fast Barriers For A Shared-Memory Cluster Of 1024 RISC-V Cores
By Technical Paper Link - 27 Jul, 2023 - Comments: 0

A technical paper titled “Fast Shared-Memory Barrier Synchronization for a 1024-Cores RISC-V Many-Core Cluster” was published by researchers at ETH Zürich and Università di Bologna. "Synchronization is likely the most critical performance killer in shared-memory parallel programs. With the rise of multi-core and many-core processors, the relative impact on performance and energy overhe... » read more

RISC-V Open Platform for Next-Gen Automotive ECUs (ETH Zurich, Huawei)
By Technical Paper Link - 27 Jul, 2023 - Comments: 0

A technical paper titled “Towards a RISC-V Open Platform for Next-generation Automotive ECUs” was published by researchers at ETH Zurich and Huawei Research Center (Italy). Abstract: "The complexity of automotive systems is increasing quickly due to the integration of novel functionalities such as assisted or autonomous driving. However, increasing complexity poses considerable challenges... » read more

Demonstrating The Capabilities Of Virtual Wafer Process Modeling And Virtual Metrology
By Technical Paper Link - 27 Jul, 2023 - Comments: 0

A technical paper titled “Review of virtual wafer process modeling and metrology for advanced technology development” was published by researchers at Coventor Inc., Lam Research. Abstract: "Semiconductor logic and memory technology development continues to push the limits of process complexity and cost, especially as the industry migrates to the 5 nm node and beyond. Optimization of the p... » read more

A Flip-Chip, Co-Packaged With Photodiode, High-speed TIA in 16nm FinFET CMOS
By Technical Paper Link - 20 Jul, 2023 - Comments: 0

A technical paper titled "A 112-Gb/s —8.2-dBm Sensitivity 4-PAM Linear TIA in 16-nm CMOS With Co-Packaged Photodiodes" was published by researchers at University of Toronto, Alphawave IP, and Huawei Technologies Canada. Abstract: "A flip-chip co-packaged linear transimpedance amplifier (TIA) in 16-nm fin field effect transistor (FinFET) CMOS demonstrating 112-Gb/s four-level pulse-amplitude... » read more

NoC Obfuscation For Protecting Against Reverse Engineering Attacks (U. Of Florida)
By Technical Paper Link - 20 Jul, 2023 - Comments: 0

A technical paper titled "ObNoCs: Protecting Network-on-Chip Fabrics Against Reverse-Engineering Attacks" was published by researchers at University of Florida. Abstract: "Modern System-on-Chip designs typically use Network-on-Chip (NoC) fabrics to implement coordination among integrated hardware blocks. An important class of security vulnerabilities involves a rogue foundry reverse-engineeri... » read more

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