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Applications Of Large Language Models For Industrial Chip Design (NVIDIA)
By Technical Paper Link - 10 Nov, 2023 - Comments: 0

A technical paper titled “ChipNeMo: Domain-Adapted LLMs for Chip Design” was published by researchers at NVIDIA. Abstract: "ChipNeMo aims to explore the applications of large language models (LLMs) for industrial chip design. Instead of directly deploying off-the-shelf commercial or open-source LLMs, we instead adopt the following domain adaptation techniques: custom tokenizers, domain-ad... » read more

A Novel Approach To Mitigating RowHammer Attacks And Improving Server Memory System Reliability
By Technical Paper Link - 07 Nov, 2023 - Comments: 0

A technical paper titled “RAMPART: RowHammer Mitigation and Repair for Server Memory Systems” was published by researchers at Rambus. Abstract: "RowHammer attacks are a growing security and reliability concern for DRAMs and computer systems as they can induce many bit errors that overwhelm error detection and correction capabilities. System-level solutions are needed as process technology... » read more

CMOS-Based HW Topology For Single-Cycle In-Memory XOR/XNOR Operations
By Technical Paper Link - 07 Nov, 2023 - Comments: 0

A technical paper titled “CMOS-based Single-Cycle In-Memory XOR/XNOR” was published by researchers at University of Tennessee, University of Virginia, and Oak Ridge National Laboratory (ORNL). Abstract: "Big data applications are on the rise, and so is the number of data centers. The ever-increasing massive data pool needs to be periodically backed up in a secure environment. Moreover, a ... » read more

Modulated Electron Microscopy Applied In The Process Monitoring Of Memory Cell And The Defect Inspection Of Floating Circuits
By Technical Paper Link - 07 Nov, 2023 - Comments: 0

A technical paper titled “In situ electrical property quantification of memory devices by modulated electron microscopy” was published by researchers at Hitachi High-Tech Corporation, KIOXIA Corporation, and Western Digital. Abstract: "E-beam inspection based on voltage-contrast (VC) defect metrology has been widely utilized for failure mode analysis of memory devices. Variation in e-beam... » read more

Discrete Noise Approximation When Modeling The Effects Of Noise On Quantum Circuits
By Technical Paper Link - 07 Nov, 2023 - Comments: 0

A technical paper titled “The Discrete Noise Approximation in Quantum Circuits” was published by researchers at HQS Quantum Simulations. Abstract: "When modeling the effects of noise on quantum circuits, one often makes the assumption that these effects can be accounted for by individual decoherence events following an otherwise noise-free gate. In this work, we address the validity of th... » read more

A Survey Of Recent Advances And Research Activities In Wireless NoC Security
By Technical Paper Link - 07 Nov, 2023 - Comments: 0

A technical paper titled “Wireless Network-on-Chip Security Review: Attack Taxonomy, Implications, and Countermeasures” was published by researchers at Macquarie University (Sydney). Abstract: "Network-on-chip (NoC) is a critical on-chip communication framework that underpins high-performance multicore computing and network system architectures. Its adoption has become widespread due to t... » read more

Improving The Retention Characteristics Of 3D NAND Flash Memories
By Technical Paper Link - 31 Oct, 2023 - Comments: 0

A technical paper titled “3D NAND Flash Memory Cell Current and Interference Characteristics Improvement With Multiple Dielectric Spacer” was published by researchers at Myongji University, Soongsil University, and Seoul National University. Abstract: "To achieve high density, the spacer length of three dimensional (3D) NAND device has been scaled down. When the program/erase cycle repeat... » read more

A New Architecture And Verification Approach For Hardware Security Modules
By Technical Paper Link - 31 Oct, 2023 - Comments: 0

A technical paper titled “The K2 Architecture for Trustworthy Hardware Security Modules” was published by researchers at MIT Computer Science and Artificial Intelligence Laboratory (CSAIL) and New York University. Abstract: "K2 is a new architecture and verification approach for hardware security modules (HSMs). The K2 architecture's rigid separation between I/O, storage, and computation ... » read more

Potentials And Issues Of Designing Fault-Tolerant Hardware Acceleration For Edge-Computing Devices
By Technical Paper Link - 31 Oct, 2023 - Comments: 0

A technical paper titled “Fault-Tolerant Hardware Acceleration for High-Performance Edge-Computing Nodes” was published by researchers at University of Rome. Abstract: "High-performance embedded systems with powerful processors, specialized hardware accelerators, and advanced software techniques are all key technologies driving the growth of the IoT. By combining hardware and software tec... » read more

A Modelling Approach To Well-Known And Exotic 2D Materials For Next-Gen FETs
By Technical Paper Link - 31 Oct, 2023 - Comments: 0

A technical paper titled “Field-Effect Transistors based on 2-D Materials: a Modeling Perspective” was published by researchers at ETH Zurich. Abstract: "Two-dimensional (2D) materials are particularly attractive to build the channel of next-generation field-effect transistors (FETs) with gate lengths below 10-15 nm. Because the 2D technology has not yet reached the same level of maturity... » read more

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