Author's Latest Posts

Chip Sandwich: Electronics Chip & Photonics Chip Co-Optimized To Work Together (CalTech/Univ. of Southampton)
By Technical Paper Link - 01 Dec, 2022 - Comments: 0

A technical paper titled "A 100-Gb/s PAM4 Optical Transmitter in a 3-D-Integrated SiPh-CMOS Platform Using Segmented MOSCAP Modulators" was published by researchers at CalTech and University of Southampton. "The resulting optimized interface between the two chips allows them to transmit 100 gigabits of data per second while producing just 2.4 pico-Joules per transmitted bit. This improves th... » read more

HW Accelerator Architecture for MI Computation With Low Latency, Energy Efficient (MIT)
By Technical Paper Link - 01 Dec, 2022 - Comments: 0

A new technical paper titled "Efficient Computation of Map-scale Continuous Mutual Information on Chip in Real Time" was published by researchers at MIT. Find the technical paper here. "In this paper, we introduce a new hardware accelerator architecture for MI computation that features a low-latency, energy-efficient MI compute core and an optimized memory subsystem that provides sufficie... » read more

MAC Operation on 28nm High-k Metal Gate FeFET-based Memory Array with ADC (Fraunhofer IPMS/GF)
By Technical Paper Link - 01 Dec, 2022 - Comments: 0

A technical paper titled "Demonstration of Multiply-Accumulate Operation With 28 nm FeFET Crossbar Array" was published by researchers at Fraunhofer IPMS and GlobalFoundries. Abstract "This letter reports a linear multiply-accumulate (MAC) operation conducted on a crossbar memory array based on 28nm high-k metal gate (HKMG) Complementary Metal Oxide Semiconductor (CMOS) and ferroelectric fi... » read more

Using Sparseloop in Hardware Accelerator Design Flows (MIT)
By Technical Paper Link - 30 Nov, 2022 - Comments: 0

A technical paper titled "Sparseloop: An Analytical Approach To Sparse Tensor Accelerator Modeling" was published by researchers at MIT and NVIDIA.  The paper won "Distinguished Artifact Award" at the MICRO 2022 conference. Find the technical paper here.  Published 2022.  Project website is here and github here. Abstract: "In recent years, many accelerators have been proposed to effici... » read more

Optimizing Hardware Capacity, Utilizing Automatic Differentiation to Efficiently Compute Derivatives in Parallel Programming Models
By Technical Paper Link - 30 Nov, 2022 - Comments: 0

A technical paper titled "Scalable Automatic Differentiation of Multiple Parallel Paradigms through Compiler Augmentation" was published by researchers at MIT (CSAIL), Argonne National Lab, and TU Munich. The paper was a Best Paper Finalist and a Best Student Paper winner at SuperComputing 2022. Find the technical paper here. Published November 2022. The work "demonstrates how Enzyme opti... » read more

Connecting Quantum Devices With Sound
By Technical Paper Link - 30 Nov, 2022 - Comments: 0

A new technical paper titled "On-chip distribution of quantum information using traveling phonons" was published by researchers at TU Delft, Center for Nanophotonics, AMOLF, and Eindhoven University of Technology. "Physicists from the Gröblacher lab at TU Delft have built a device that can link different quantum devices and qubits to each other. This device, a silicon chip with vibrations t... » read more

Capability Hardware Enhanced RISC Instructions (CHERI) For Verification, With Better Memory Safety (Oxford)
By Technical Paper Link - 30 Nov, 2022 - Comments: 0

A technical paper titled "A Formal CHERI-C Semantics for Verification" was published by researchers at University of Oxford. Abstract: "CHERI-C extends the C programming language by adding hardware capabilities, ensuring a certain degree of memory safety while remaining efficient. Capabilities can also be employed for higher-level security measures, such as software compartmentalization, ... » read more

3D Structuring Inside GaAs by Ultrafast Laser Inscription
By Technical Paper Link - 28 Nov, 2022 - Comments: 0

A new technical paper titled "Burst mode enabled ultrafast laser inscription inside gallium arsenide" was published by researchers at LP3 Laboratory in France, a joint research unit of Aix-Marseille University (AMU) and CNRS. "We investigate the possibility of using THzrepetition-rate burst mode for ULI inside GaAs, a material that cannot be internally processed with single femtosecond pulse... » read more

Phononic and Magnonic Properties of 1D MoI3 Nanowires
By Technical Paper Link - 28 Nov, 2022 - Comments: 0

A new technical paper titled "Elemental excitations in MoI3 one-dimensional van der Waals nanowires" was published by researchers at NIST, UC Riverside, University of Georgia, Theiss Research Inc, and Stanford University. "We described here the elemental excitations in crystals of MoI3 a vdW [van der Waals] material with a true-1D crystal structure. Our measurements reveal anomalous temperat... » read more

Wafer-Scale Variability In Photonic Devices & Effects On Circuits
By Technical Paper Link - 25 Nov, 2022 - Comments: 0

A technical paper titled "Capturing the Effects of Spatial Process Variations in Silicon Photonic Circuits" was published by researchers at Photonics Research Group, Ghent University−IMEC. "We present in this paper a method to extract a granular map of the line width and thickness variation on a silicon photonics wafer. We propose a hierarchical model to separate the layout-dependent and l... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy