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Mask Data Preparation Flow For Advanced Technology Nodes
By Various Writers - 18 Apr, 2013 - Comments: 0

The trend to reduce critical features dimension has dramatically increased design file size. Design tape–out flows at the 28 nm technology node handle post-OPC data files that reach hundreds of gigabytes. This trend increases at 20 nm and below. That predicts new challenges in mask data preparation flow for advanced technology nodes. We have developed a mask data preparation flow to tackle th... » read more

GF’S Two Flavors Of FD-SOI
By Various Writers - 17 Apr, 2013 - Comments: 0

Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News ~  ~ Hearing the news that GlobalFoundries would be offering two flavors of FD-SOI, ASN asked the company to explain the strategy further. Here are the responses provided by Subi Kengeri, Vice President of Advanced Technology Architecture.   [caption id="" align="alignleft" width="110"] Subi Kengeri, VP Advanced T... » read more

RTL Restructuring
By Various Writers - 11 Apr, 2013 - Comments: 0

We all know that hierarchy created for logic design must often be adjusted to map to a physical implementation. Logic hierarchy is typically constrained by non-implementation factors, especially organization of teams working on different components and use of legacy or 3rd party IP. Physical hierarchy, on the other hand, must partition the logic to fit detailed implementation tool capacity limi... » read more

Optimizing Cost-Performance-Schedule With A Chip-Package-System (CPS) Methodology
By Various Writers - 11 Apr, 2013 - Comments: 0

To meet smart device requirements with high levels of sophistication from an exceedingly small device running off a battery, the underlying electronics must evolve at a rapid pace. To read more, click here. » read more

How To Reduce The Need For Guardbanding A Flash ADC Design
By Various Writers - 28 Mar, 2013 - Comments: 0

For sensitive mixed-signal designs at small process nodes, the influence of parasitic elements is growing with the increasing interactions among devices and interconnects that are in close proximity. Circuits are highly sensitive to these parasitic effects, and accurate parasitic extraction is critical for first silicon success. New 3D parasitic extraction technology applied to a flash ADC circ... » read more

Solutions For Mixed-Signal SoC Verification
By Various Writers - 28 Mar, 2013 - Comments: 0

Performing full-chip verification of large mixed-signal systems on chip (SoCs) is an increasingly daunting task. As complexity grows and process nodes shrink, it’s no longer adequate to bolt together analog or digital “black boxes” that are presumed to be pre-verified. Complex analog/ digital interactions can create functional errors, which delay tapeouts and lead to costly silicon re-spi... » read more

Solutions For Mixed-Signal IP, IC, And SoC Implementation
By Various Writers - 28 Mar, 2013 - Comments: 0

Traditional mixed-signal design environments, in which analog and digital parts are implemented separately, are no longer sufficient and lead to excess iteration and prolonged design cycle time. Realizing modern mixed-signal designs requires new flows that maximize productivity and facilitate close collaboration among analog and digital designers. This paper outlines mixed-signal implem... » read more

Physical Verification Of FinFETs And Fully Depleted SOI
By Various Writers - 28 Mar, 2013 - Comments: 0

It has become very difficult to effectively shrink traditional bulk planar transistors below 20nm due to physical effects that become dominant in very short conduction channels. The major impediment is an unacceptable rise in power consumption due to significant leakage currents. New transistor architectures are being adopted that offer a solution for these short-channel effects and allow trans... » read more

Computational Lithography
By Various Writers - 21 Mar, 2013 - Comments: 0

Computational lithography has become an integral part of design since the 130 nm process node. New techniques continue to be developed to extend the steady node shrink year after year. To read this white paper, click here. » read more

Next-Generation Signoff Analysis
By Various Writers - 21 Mar, 2013 - Comments: 0

The electronic design industry continues to push the limits of moore's law through smaller and smaller process nodes. As we reach 45nm, manufacturing and process control becomes increasingly difficult, making it imperative that manufacturability issues be addressed much earlier in the design cycle to avoid costly respins and chip failures. Physical and electrical effects at this node challen... » read more

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