Best practices for tackling electrical, physical and manufacturing challenges.
The electronic design industry continues to push the limits of moore’s law through smaller and smaller process nodes. As we reach 45nm, manufacturing and process control becomes increasingly difficult, making it imperative that manufacturability issues be addressed much earlier in the design cycle to avoid costly respins and chip failures.
Physical and electrical effects at this node challenge both design closure and time to market, and the requirements for design signoff are changing in order to address the inherent manufacturing and process variability. Naturally, this situation can seriously undermine the manufacturability of the design. In fact, a paradigm shift is evident in the all-important signoff analysis step of the digital design cycle.
At issue are the levels of validity and confidence that can be reached with today’s Ic design closure and signoff methodologies. designs that pass traditional sign-off standards might still fail in 45nm silicon. In contrast, using excessive guard-bands or over-conservative margins to satisfy traditional static timing analysis (sTA) signoff regimes can negate the benefits that smaller process geometries offer.
This paper looks at some of the electrical, physical, and manufacturing challenges to current signoff analysis methods, and shows new ways to improve predictability, productivity and performance at the 45nm process node. using these new methodologies, designers can prevent silicon failures and better manage timing, leakage power, and signal integrity–both across a wafer and across the surface of a single chip.
 |
 |
 |
 |
 |
 |
 |  |
Leave a Reply