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RTL Design-For-Power Methodology
By Various Writers - 14 Feb, 2013 - Comments: 0

This white paper presents a design-for-power methodology, beginning early in the design process at the RTL-level for maximum impact on power. To download this white paper, click here. » read more

Power Benefits Of Modular Interconnect Design Using Network-On-Chip Technology
By Various Writers - 31 Jan, 2013 - Comments: 0

The system-on-chip (SoC) interconnect spans the entire floorplan of a chip and consumes a significant portion of the power. The interconnects of today’s SoCs are a distributed architecture of switches, buffers, firewalls, register slices, and clock and power domain crossings. One approach is to implement these units modularly with a simple, universal transport protocol between all units. This... » read more

The Integrated IP Subsystem: A Converging SoC Solution
By Various Writers - 31 Jan, 2013 - Comments: 0

The consumer device market is witnessing incredible market space convergence between mobile handheld, automotive, and home electronics. IP vendors, engineers, and system design engineers face a multitude of challenges when designing and developing ICs, systems, or subsystems for the next great portable device. The next cell phone for instance, will not only be a multimedia player, but also a de... » read more

Managing Functional Verification Projects
By Various Writers - 31 Jan, 2013 - Comments: 0

The adoption of advanced verification languages and methodologies requires evolution of project management techniques in addition to the change in engineering practices. Managers must be able to assess and manage key project elements such as team expertise, verification methodology, verification IP (VIP) selection and environment setup to successfully deploy high-level verification environments... » read more

Mixed-Signal Technology Summit Proceedings
By Various Writers - 31 Jan, 2013 - Comments: 0

On September 20 Cadence held the second Mixed-Signal Technology Summit. Experts from Cadence and other leading companies presented the latest mixed-signal design methodologies. If you missed the event, you can still view the material via the below archived proceedings. To view the presentations and videos, click here. » read more

Calibre RealTime: Placing Signoff Verification into the Custom Designer’s Hands
By Various Writers - 24 Jan, 2013 - Comments: 0

How to reduce custom/AMS design cycle time while improving design quality with on-demand, in-design, signoff-quality verification from Calibre RealTime. To download this white paper, click here. » read more

ST-Ericsson’s 28nm FD-SOI Smartphone/ Tablet Chip
By Various Writers - 24 Jan, 2013 - Comments: 0

By Adele Hars In the last blog, we kicked off what promises to be an exciting year with the news that ST-Ericsson announced the NovaThorL8580 ModAp. It’s billed as “the world’s fastest and lowest-power integrated LTE smartphone platform,” is built on STMicroelectronics’ 28nm FD-SOI, and is sampling in Q1 2013. We said it was a game changer, and ST-E’s put together a really good... » read more

ST-Ericsson 28nm FD-SOI/ARM Chip Hits 2.8GHz at CES
By Various Writers - 22 Jan, 2013 - Comments: 0

Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News ~  ~ What a great start to 2013: at CES in Las Vegas, ST-Ericsson announced the NovaThor™ L8580 ModAp, “the world’s fastest and lowest-power integrated LTE smartphone platform.” This is the one that’s on STMicroelectronics’ 28nm FD-SOI, with sampling set for Q1 2013. And it’s a game changer – for users, fo... » read more

ANSYS And Apache Technologies For An Integrated Chip-Package-System Flow
By Various Writers - 17 Jan, 2013 - Comments: 0

This paper presents solutions for effectively managing design specifications (performance) and margins (price). It discusses solutions based on accurate and predictive simulation software from ANSYS and Apache that offers electronics designers a simulation-driven chip–package–system convergence methodology. To download this white paper, click here. » read more

Designing With FinFETs: The Opportunities And The Challenges
By Various Writers - 29 Dec, 2012 - Comments: 0

With the help of double-patterning and other advanced lithography techniques, CMOS technology continues to scale to 20-nanometer (nm) and beyond. Yet, because of their superior attributes, FinFETs are replacing planar CMOS technology as the device technology of choice at these advanced nodes. In particular, FinFETs demonstrate better results in the areas of performance, leakage and dynamic powe... » read more

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