ST-Ericsson’s 28nm FD-SOI Smartphone/ Tablet Chip

More body biasing than bulk, higher speeds, lower operating voltages and optimal combinations. It’s a game-changer.

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By Adele Hars
In the last blog, we kicked off what promises to be an exciting year with the news that ST-Ericsson announced the NovaThorL8580 ModAp. It’s billed as “the world’s fastest and lowest-power integrated LTE smartphone platform,” is built on STMicroelectronics’ 28nm FD-SOI, and is sampling in Q1 2013.

We said it was a game changer, and ST-E’s put together a really good page on their website that shows how they’re doing it.

By way of reminder, the NovaThor L8580 integrates an eQuad 2.5GHz processor (the mobile industry’s fastest) based on an ARM Cortex-A9, an Imagination PowerVR SGX544 GPU running at 600Mhz and an advanced multimode LTE modem on a single 28nm FD-SOI die.

The ST-E site is well worth looking at yourself – but in the meantime, here are a few of the highlights they’re sharing:

* With FD-SOI, you can do much more with body-biasing (aka back-biasing) than you can in bulk (which suffers from too much leakage). Thanks to the ultra-thin insulator layer in FD-SOI, the biasing creates a buried gate below the channel, so it effectively acts like a vertical double gate transistor. This facilitates the flow of electrons, leading to a higher voltage in the body, and faster switching of the transistor.

(Courtesy: ST-Ericsson)

* With FD-SOI, you can hit higher speeds with lower operating voltages. This is because the buried oxide layer prevents electrons from leaking away as they travel through the channel from the source to the drain (this sort of leakage is a major source of power consumption in 28nm bulk, which depends on doping to handle leakage). Interestingly, this graph shows ST-E going down to 0.5V – which is incredibly impressive.

(Courtesy: ST-Ericsson)

* As the (now award-winning) folks over at ST and Leti described for us a few years ago, designing a good SOC involves using the right blend of low, standard and high-Vt devices according to the target application and how it’s being used at any given time. The ST-E designers use this feature to apply different voltages independently to the top and the buried gates of the FD-SOI transistor, which effectively changes its characteristics. By choosing optimal combinations of the voltages, the transistor characteristics can be transformed from those of a very high-performance transistor to those of a very low-power transistor. A processing core built up of such transistors can operate as if it were in fact two cores – one optimized for high performance and the other for low power. (You can’t do this with FinFETs, btw.)

(Courtesy: ST-Ericsson)

Now are you starting to see why it’s a game changer?

—Adele Hars is the editor in chief of Advanced Substrate News.