Author's Latest Posts

Meeting Emerging Needs For Next-Generation 3D-IC And Sub-20nm Designs
By Various Writers - 09 Aug, 2012 - Comments: 0

To remain competitive, IC designers must meet performance, power and price goals. However, these mutually conflicting goals require design techniques including 3D stacked-die architectures that will help meet performance and power targets by extending the integration capabilities beyond traditional SoC methodologies. To download this white paper, click here. » read more

Designing into A Foundry Low-Power High-k Metal Gate 28nm CMOS Solution
By Various Writers - 31 Jul, 2012 - Comments: 0

28nm Super Low Power is the low power CMOS offering delivered on a bulk silicon substrate for mobile consumer and digital consumer applications. The 28nm process technology is slated to become the foundation for a new generation of portable electronics that are capable of handling streaming video, data, voice, social networking and mobile commerce applications. To view this white paper, clic... » read more

Multi-Source CTS Delivers Flexible High Performance and Variation Tolerance
By Various Writers - 26 Jul, 2012 - Comments: 0

Multi-source clock tree is a hybrid containing the best aspects of a conventional clock tree and a pure clock mesh. This paper illustrates the benefits such as lower skew and better on-chip-variation (OCV) performance compared to a conventional clock tree. To download this white paper, click here. » read more

Achieving Fast And Accurate Extraction Of 3D-IC Layout Structures
By Various Writers - 26 Jul, 2012 - Comments: 0

The electronics industry is devoting a lot of energy to exploring “More than Moore’s Law” approaches that drive continued value scaling through system integration, rather than (or in addition to) shrinking transistors. One of the most promising techniques is the creation of 3D-ICs using TSV structures. However, accurately modeling a 3D multi-die system requires tools that extract precise ... » read more

Bringing Continuous Domain Into SystemVerilog Covergroups
By Various Writers - 26 Jul, 2012 - Comments: 0

This paper proposes a set of requirements for specifying functional coverage on an analog or mixed-signal block. We explain how the real number data type can be introduced in the [gettech id="31023" comment="SystemVerilog"] coverpoint specification and how it can enable a complete coverage specification for a mixed-signal verification environment. In discussing the requirements, we explore the... » read more

Leti Looks at Using Strain with FD-SOI for High-Perf Apps
By Various Writers - 29 Jun, 2012 - Comments: 0

The researchers at Leti working on FD-SOI have extremely deep expertise in it. One of the areas they've looked at is performance boosters. With the interest in FD-SOI rapidly increasing on the heels of the recent ST-GF announcement, their work becomes even more timely. A key Leti team wrote a summary of some recent strain work, which first appeared as part of the Advanced Substra... » read more

High Speed PCB Layout: Physical Design Issues Of Highspeed Interfaces
By Various Writers - 28 Jun, 2012 - Comments: 0

Moore’s law, applied to data rates, has pushed PCB circuits so fast that the layout becomes part of the circuit. In designs such as DDR3 and PCIe, the fastest memory and high-speed serial performance comes with very specific physical layout requirements that are not obvious. Unless you are thinking like an RF designer, there are many unexpected challenges to a successful high-speed layout. A ... » read more

PSL/SVA Assertions In SPICE
By Various Writers - 28 Jun, 2012 - Comments: 0

Assertion-based verification is a key aspect of any complete SoC or Silicon Realization flow. In this paper, we discuss how PSL (Property Specification Language)/SVA (System-V erilog Assertions) assertion semantics are extended for the first time to SPICE (Simulation Program with Integrated Circuit Emphasis)-level netlists and evaluated within a SPICE simulator, and present multiple examples an... » read more

Technical Considerations For Implementing USB 3.0 On SoCs
By Various Writers - 28 Jun, 2012 - Comments: 0

The Universal Serial Bus (USB) protocol has been the standard way to connect computers to external devices for nearly two decades. The protocol continues to evolve to support the growing demands of consumer devices. With its simplicity of use, USB is the number one choice of connectivity protocols in the consumer world. USB 3.0 early adoption began in 2010. Now, key USB software and systems pro... » read more

The Challenges Of 28nm HKMG
By Various Writers - 26 Jun, 2012 - Comments: 0

28nm Super Low Power (28nm-SLP) is the low power CMOS offering delivered on a bulk silicon substrate for mobile consumer and digital consumer applications. This technology has four Vt's (high, regular, low and super low) for design flexibility with multi-channel length capability and offers the ultimate in small die size and low cost. Multiple SRAM bit cells for high density and high-performanc... » read more

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