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UVM Do’s And Don’ts For Effective Verification
By Various Writers - 24 May, 2012 - Comments: 0

With more than a year of production use, the Accellera Systems Initiative UVM is now clearly the methodology of choice for verification. The rush to adopt UVM has both matured the BCL quickly, producing UVM 1.1 and 1.1a bug-fix versions, as well as created a wealth of institutional know-how. Of course, the challenge with know-how is that it tends to be distributed among all the members of the c... » read more

Audio Subsystems For Efficient SoC Integration
By Various Writers - 24 May, 2012 - Comments: 0

Implementing advanced audio functionality in a system-on-chip (SoC) involves integrating a range of hardware and software components, including an audio processor, audio peripherals, software drivers, and audio processing software. In this white paper, we discuss the requirements for audio solutions for processing of high-definition (HD) multi-channel audio and detail the challenges involved in... » read more

NoC Power Benefits
By Various Writers - 24 May, 2012 - Comments: 0

The system-on-chip (SoC) interconnect spans the entire floorplan of a chip and consumes a significant portion of the power. The interconnects of today’s SoCs are a distributed architecture of switches, buffers, firewalls, register slices, and clock and power domain crossings. One approach is to implement these units modularly with a simple, universal transport protocol between all units... » read more

Understanding Via Effects
By Various Writers - 24 May, 2012 - Comments: 0

As the demand for fast computation and information transmission has increased dramatically in recent years, many designs have boards with signals operating in the multiple-Gbps range. Advanced memory designs are targeting over 10 Gbps data rates while the SERDES standard is moving toward 25-28 Gbps. With the signal speed changes come the new challenges of solving design issues never seen before... » read more

High-End Audio Made Easy: The Software Story
By Various Writers - 25 Apr, 2012 - Comments: 0

Audio requirements are soaring. Whereas audio used to be done in a few spare cycles of the main CPU, decoding today’s Blu-ray Disc 24-bit, 192 kHz high-definition audio streams, or post-processing 9.1 channel Pro Logic IIz streams, requires significant performance. An obvious solution is to offload the processing to one or more dedicated audio digital signal processors (DSPs) such as the Desi... » read more

Power Benefits Of Modular Interconnect Design Using Network-On-Chip Technology
By Various Writers - 25 Apr, 2012 - Comments: 0

The system-on-chip (SoC) interconnect spans the entire floorplan of a chip and consumes a significant portion of the power. The interconnects of today’s SoCs are a distributed architecture of switches, buffers, firewalls, register slices, and clock and power domain crossings. One approach is to implement these units modularly with a simple, universal transport protocol between all units. This... » read more

ST-Ericsson 28nm FD-SOI smartphone SOC, Q3 tape-out (interview)
By Various Writers - 24 Apr, 2012 - Comments: 0

ASN recently had a chance to talk to ST-Ericsson’s Chief Chip Architect Louis Tannyeres  about the move to 28nm FD-SOI for smartphones and tablet SOCs.  Take-away message:  FD-SOI solves – with less process complexity – scaling, leakage and variability issues to further shrink CMOS technology beyond 28nm. Here's what he said. ~~ [caption id="attachment_441" align="alignleft" wi... » read more

PathFinder Solution For Full-Chip IC ESD Integrity
By Various Writers - 05 Apr, 2012 - Comments: 0

This paper describes how PathFinder helps designers meet ESD guidelines and identify “weak” areas of the design (layout or circuit) most vulnerable to ESD failures. It also demonstrates how PathFinder can be used for early prototyping and design exploration, especially when clamp cells are inserted inside the core region of the chip. To download this white paper, click here. » read more

Consortium Results (Part 3 of 3): 20nm FDSOI Comes Out Way Ahead
By Various Writers - 27 Mar, 2012 - Comments: 0

The results of the most recent SOI Consortium benchmarking study detail the interest of planar FD-SOI as early as the 28nm and 20nm technology nodes, in terms of performance, power and manufacturability. This 3-part blog series looks further at some of the implications. ~~ The SOI Industry Consortium announcement at the end of the year provided silicon proof that FD-SOI handily bea... » read more

FD-SOI – Consortium Results (Part 2 of 3): Power and Performance
By Various Writers - 21 Mar, 2012 - Comments: 0

The results of the most recent SOI Consortium benchmarking study detail the interest of planar FD-SOI as early as the 28nm and 20nm technology nodes, in terms of performance, power and manufacturability. This 3-part blog series looks further at some of the implications. ~~ Fully depleted transistor architectures such as Planar FD-SOI, FinFETs (which is also a fully-depleted technolog... » read more

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