Systems & Design

UVM Do’s And Don’ts For Effective Verification

Best practices for using the register package, how and where to use the objection mechanism, and configuration tips.


With more than a year of production use, the Accellera Systems Initiative UVM is now clearly the methodology of choice for verification. The rush to adopt UVM has both matured the BCL quickly, producing UVM 1.1 and 1.1a bug-fix versions, as well as created a wealth of institutional know-how. Of course, the challenge with know-how is that it tends to be distributed among all the members of the community with little pearls appearing in various forums and contributions. While many sessions introduce the UVM to new users or specific aspects of it for advanced users, the critical tips and best practices are often diffused throughout that material if they are presented at all. So for all of the verification engineers that have been working this year and thought “I wonder if this is the best approach” or “should I use this UVM feature”, this presentation cuts right to the answer with specific pointers and code examples, gathered from live projects worldwide, that you can use immediately for more effective verification.

To view this white paper, click here.


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