PathFinder Solution For Full-Chip IC ESD Integrity

How to identify weak areas of the layout or circuit that are most vulnerable to ESD failures.

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This paper describes how PathFinder helps designers meet ESD guidelines and identify “weak” areas of the design (layout or circuit) most vulnerable to ESD failures. It also demonstrates how PathFinder can be used for early prototyping and design exploration, especially when clamp cells are inserted inside the core region of the chip.

To download this white paper, click here.