Author's Latest Posts

RTL Design For Power Methodology
By Various Writers - 21 Jul, 2011 - Comments: 0

This power budgeting white paper presents a design-for-power methodology, starting early in the design process at the Register Transfer Level (RTL), to help deliver maximum impact on power. To download this white paper, click here. » read more

New Wii U™ on SOI
By Various Writers - 08 Jul, 2011 - Comments: 0

By Adele Hars If you've followed the industry buzz in recent weeks, you've seen the news: the CPU for Nintendo's upcoming (and very cool) Wii U is on IBM's 45nm SOI. IBM's been fabbing chips for Nintendo for over a decade, and first moved the company's CPUs to SOI in 2006, at 90nm. The Wii U, which got its debut at the recent E3 show, will hit the shelves in 2012. The Wii U combines m... » read more

Congestion Mitigation During RTL Development
By Various Writers - 29 Jun, 2011 - Comments: 0

Any survey of chip design teams consistently points to two problem areas impacting quality and schedule of today’s system on chip (SoC) designs. Those areas are: a) completeness of verification, and b) physical design closure for area, timing and power for complex IP’s and SoC’s. With the advent of deep sub-micron technology, these problem areas have become exacerbated. In this White Pape... » read more

Smart Power on SOI
By Various Writers - 06 Jun, 2011 - Comments: 0

By Adele Hars What if you had to reduce power dissipation by 40x? That's exactly the task that fell to STMicroelectronics, under an EU program called Smart Power Management. At the recent ISPSD (International Symposium on Power Semiconductor Devices and ICs) conference, ST and partners (GE Vingmed Ultrasound and Sintef) presented a paper on how they did it, using ST's latest SOI-based ... » read more

RF Substrate Technologies for Mobile Communications
By Various Writers - 23 May, 2011 - Comments: 0

Two Soitec Group managers -- Eric Desbonnets and Stéphane Laurent -- describe how SOI wafers support RF technology development. » read more

FD-SOI: The Right Choice
By Various Writers - 20 May, 2011 - Comments: 0

By Adele Hars Although Intel will do FinFETs at 22nm, FD-SOI remains the better alternative for most all the industry for low power and mobile apps. In the weeks and months to come, we'll continue to hear the SOI camp driving home key advantages of planar FD-SOI. 1. FD-SOI technology is the most cost-effective solution. The wafers are available from multiple sources. With volume purchasi... » read more

Power Noise Analysis For Next Generation ICs
By Various Writers - 12 May, 2011 - Comments: 0

In advanced technology nodes, SoC designs face complex power supply challenges driven by changes such as higher gate placement density, smaller wire and via geometries, and lower supply voltages in sophisticated, multi-layered packages and boards. The challenges associated with power delivery networks (PDN) anywhere on the die, package and board designs can be seen in all types of ICs, includin... » read more

SoC Realization: The Linchpin To Enabling Electronics Innovation
By Various Writers - 11 May, 2011 - Comments: 0

There are significant changes occurring in the electronics industry. The widespread consumerization of electronic devices has permanently changed our lives for the better. The rate at which hand-held, personal electronic products are evolving is staggering by any historical measure. These rapid advances are facilitated by system on chip (SoC) devices, the microelectronic marvels of engineering ... » read more

Understanding Formal Verification Concepts
By Various Writers - 28 Apr, 2011 - Comments: 0

In today’s complex system on chip (SoC) designs, verification has become a real challenge. Register transfer level (RTL) and gate-level simulations are effectively used for verifying the functional correctness of any design. However, as designs are growing in size as well as functionality, more and more test vectors need to be created and run to get reasonable test coverage. In addition to th... » read more

Advanced Modeling Technologies For Chip, Package, System Co-Analysis And Co-Optimization
By Various Writers - 14 Apr, 2011 - Comments: 0

The traditional approach to chip-package-system (CPS) co-analysis and co-optimization lacks required accuracy and limits productivity. To meet the increasing demands for system cost down calls for a new methodology that is more comprehensive. This white paper outlines the Chip Power Model (CPMT) technologies and solutions available from Apache Design Solutions to help address the CPS convergenc... » read more

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