Power Noise Analysis For Next Generation ICs

New considerations for 3D stacking and for high-performance and low-power circuits.

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In advanced technology nodes, SoC designs face complex power supply challenges driven by changes such as higher gate placement density, smaller wire and via geometries, and lower supply voltages in sophisticated, multi-layered packages and boards. The challenges associated with power delivery networks (PDN) anywhere on the die, package and board designs can be seen in all types of ICs, including low-power ICs, which have seen a surge in demand and applications due to the proliferation of handheld devices. These circuits employ several design techniques, both in the die and on the package, to control operational and standby power. The PDN design then has to contend with the transition between the various operating modes introduced by these circuit design techniques. If the package design combines several die together, either in a stacked or in a multi-chip module configuration, the impact of the presence of these various ICs have to be considered in the overall system PDN design. Devices that operate or combine elements of both high-performance and low-power circuits must address the concerns seen by both.

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