Congestion Mitigation During RTL Development

With deep sub-micron technology, completeness of verification and physical design closure have grown more problematic. Here’s how to solve these issues.

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Any survey of chip design teams consistently points to two problem areas impacting quality and schedule of today’s system on chip (SoC) designs. Those areas are: a) completeness of verification, and b) physical design closure for area, timing and power for complex IP’s and SoC’s. With the advent of deep sub-micron technology, these problem areas have become exacerbated. In this White Paper, we take a closer look at the routing congestion aspects of IP and SoC design that are impacting physical design closure.

To download this white paper, click here.


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