Author's Latest Posts


Power Delivery Network Verification Coverage


This paper presents a methodology for comprehensive power grid verification coverage, including identification of power grid weaknesses early in the design cycle. To view this white paper, click here. » read more

Reliability In Networking And Telecom Systems


The main source of heat in electronic equipment is their semiconductor chips, and the temperature sensitivities of these chips presents a challenge in designing cooling solutions. Overheating causes the chips to prematurely fail—and failure of only one chip can disable the entire equipment, the higher the chip temperature, the earlier and more certain the failure. As functionality has increas... » read more

MIMO Maximum Likelihood Detector


MIMO (Multiple Input and Multiple Output) is one of the leading approaches for improving data rates and/or SNR (Signal to Noise Ratio). By using multiple receive and transmit antennas, MIMO can exploit the diversity of the wireless channel. This is then used to increase the spectral efficiency of the channel and improve the data rates for any given channel bandwidth. This white paper reviews... » read more

Post-Silicon Validation Using Formal Analysis


Verifying the current generation of complex SoCs requires the best methodology and tools, including the application of high-capacity formal verification technologies throughout the design flow, from architectural exploration to post-silicon debug. We see this last area, post-silicon debug, as an important value delivered by formal technology for design and verification teams who have not employ... » read more

RF Periodic Stability Analysis


The PSTB (periodic stability) analysis feature in Cadence Spectre RF Simulation Option performs stability analysis for circuits with periodically time-varying operating points. PSTB is the periodic equivalent of linear stability (STB) analysis in that it calculates the small-signal loop gain, gain margin, and phase margin around a periodic operating point. PSTB is useful in applications such as... » read more

Porting To ARM 64-Bit


Why 64-bit? It seems that is a question with many answers! For some, it will be the need to address more than 4GB of memory, for others the need for wider registers and greater accuracy of 64-bit data processing, for still others the attraction of a larger register set. Whatever your reason for looking to move to 64-bit, it is likely that you will have a body of legacy software which will ne... » read more

Using Virtual Prototypes To Address The Growing Software Complexity In Automotive


The software content is growing steadily across multiple applications and the automotive market is no exception to this. In fact the amount of electronics and software in cars is transforming the way we perceive the value of a car. With this steady increase in software also comes the need to handle the amount and the complexity of all these different software stacks. And unlike other applicatio... » read more

Vista Virtual Prototyping


Vista Virtual Prototyping provides an early, abstract functional model of the hardware to software engineers even before the hardware design is implemented in RTL. It can run software on embedded processor models at speeds par with board support packages, providing sufficiently fast simulation models for OS and application software validation. The Vista Virtual Prototyping solution has two dist... » read more

Deployment of OASIS In The Semiconductor Industry


The OASIS working group was first initiated in 2001, published the new format in March 2004, which was ratified as an official SEMI standard in September 2005. A follow-on initiative expanded the new standard to cover the needs of the mask manufacturing equipment sector with a derived standard called OASIS.MASK (P44) that was released in November 2005 and updated in May 2008. While there are ma... » read more

Physical-Aware RTL Restructuring For SoC Cost Reduction


In modern SoC design, RTL hierarchy has to be manipulated throughout the entire design flow in order to accommodate different objectives at different stages of the design process. This becomes particularly true as more and more building blocks of the SoC are reused from previous designs. These requirements are driven by the need to: Adapt the RTL design hierarchy to create homogeneous subs... » read more

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