Post-Silicon Validation Using Formal Analysis

A final check of what can go wrong and how to fix it for teams that have not used formal earlier in the process.

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Verifying the current generation of complex SoCs requires the best methodology and tools, including the application of high-capacity formal verification technologies throughout the design flow, from architectural exploration to post-silicon debug. We see this last area, post-silicon debug, as an important value delivered by formal technology for design and verification teams who have not employed formal earlier in the process to get the design right the first time. As the case studies presented in this article demonstrate, the use of formal to find, fix, and verify the fix adds tremendous value in the post-silicon lab.

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