Physical-Aware RTL Restructuring For SoC Cost Reduction

A look at the needs and a recommended flow, and how this flow can be used for other purposes such as verification of subsystems.


In modern SoC design, RTL hierarchy has to be manipulated throughout the entire design flow in order to accommodate different objectives at different stages of the design process. This becomes particularly true as more and more building blocks of the SoC are reused from previous designs.
These requirements are driven by the need to:

  • Adapt the RTL design hierarchy to create homogeneous subsystems for verification
  • Group together IPs belonging to the same power domain
  • Grouping of IPs together with components of the bus fabric in order to achieve better integration density and optimum performance during physical implementation

This activity, called RTL restructuring, is an iterative process, based on evolving maturity of the RTL design. The revised version of RTL is fed into physical synthesis tools to generate the netlist for downstream floor planning and implementation.

In this paper we will focus on the needs and a recommended flow for physical-aware, RTL restructuring. The same flow can be used for other purposes like verification of sub-systems as well. To view this white paper, click here.

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