For as much as the industry focuses on automating processes, there is no replacement for the knowledge and experience of the engineer directing the tools.
We work in a dynamic industry where the focus is on making it easier to design and verify semiconductor chips by automating tasks for the design engineer. There is so much emphasis on this that I wonder if it is easy to forget the value of that designer’s experience. No matter how automated a process gets, there is always the fundamental assumption that the engineer knows what is happening behind the scenes.
I was reminded of this while discussing low power verification with Koorosh Nazifi, engineering group director for low power and mixed signal initiatives at Cadence. He explained that it is necessary to analyze IP blocks in a design to see if there are any relationships between them. If there are no relationships between two IPs at the SOC level, chances are that many of the operating modes one might have assumed from a higher level do not need to be exercised and verified. He noted that this particular part of the verification process is not automated.
As such, it is the human drawing up on their past experiences and their knowledge of this that makes the analysis complete.
Nazifi said that is key. “The whole planning process starts with a top level plan and that top-level plan becomes the spec by which you measure the outcome of your verification – that top-level plan unfortunately cannot be automated but does require human intervention. It relies on someone’s sufficient architectural knowledge of the design to basically create that top-level plan. Once that is created then we can bring in automation to extract from that top-level plan the appropriate metrics and coverage points or generate the assertions.”
So hats off to you in the design community. Please share your thoughts on this.
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