The convergence of front-end and back-end processes in advanced packaging is reshaping the industry.
The semiconductor industry is a hallmark of technological innovation, evolving rapidly to meet the demands of an increasingly digital world. At its core, semiconductor manufacturing involves two main stages: front-end processes, (wafer fabrication) and back-end processes (packaging and test). Wafer fabrication consists of creating microscopic electronic circuits on a silicon wafer. Packaging and test transform those wafers into finished chips with interconnects, ready for integration into devices like smartphones, computers, and countless other technologies.
Comparing today’s advanced semiconductor processes and manufacturing technologies with the simpler methods of the industry’s early years highlights remarkable progress driven by relentless innovation and problem-solving. The evolution of back-end packaging and test technologies and manufacturing showcases the industry’s ability to overcome formidable challenges by pushing the boundaries of what is possible.
Ken Joyce, a seasoned executive with decades of experience in back-end packaging and test operations, has witnessed transformative change from various viewpoints. As Executive Advisor at Brewer Science, Ken provides invaluable insights that help shape the company’s forward-thinking advanced packaging solutions. In a recent conversation, he shared his insights on lessons learned in packaging and the innovations shaping its future.
What are some of the most rewarding experiences from your career in packaging and test?
I consider myself incredibly fortunate to have worked alongside two visionary pioneers in the semiconductor industry: Dr. James Kim, Founder and Chairman of Amkor Technology, Inc., and Dr. Terry Brewer, Founder and Chairman of Brewer Science, Inc. These experiences have profoundly shaped my career and provided invaluable insights into the field.
One of the highlights of my career came in 2022 when I was honored to be appointed as an inaugural member of the Industrial Advisory Committee for the U.S. Department of Commerce. This committee advises on the science and technology needs of the nation’s domestic microelectronics industry, the national strategy on microelectronics research, research and development programs, and other advanced microelectronics activities funded through CHIPS for America. Additionally, the committee explores opportunities for new public-private partnerships.
From 1997 to 2013, I served in various senior leadership roles at Amkor Technology, Inc., including CFO, COO, and President & CEO, reporting directly to the company’s founder, Dr. James Kim. Dr. Kim was a true pioneer who established one of the first Outsourced Semiconductor Assembly and Test (OSAT) companies, now a global OSAT leader. During this period, we navigated several pivotal industry shifts:
The OSAT business model presented unique challenges, including razor-thin profit margins and substantial capital investment demands. In the late 2000s, we witnessed a significant shift in industry dynamics as pure-play foundries, led by TSMC, began competing in the advanced packaging market. The surging demand for smartphone digital content primarily drove this shift. Leading through these dynamic and challenging times was one of the most rewarding experiences of my career.
After my tenure at Amkor, I had the privilege of collaborating with Dr. Terry Brewer, the visionary founder of Brewer Science, Inc. Dr. Brewer was a trailblazer in developing front-end materials solutions for the photolithography phase of wafer fabrication. Over the years, he has demonstrated exceptional leadership and scientific innovation in advancing semiconductor materials research. Since 2014, I have worked under his guidance in various capacities, including as a board member, executive adviser, and interim executive for Brewer Science’s emerging business unit focused on flexible hybrid electronics. This unit develops advanced materials and devices using cutting-edge additive manufacturing processes.
Working closely with both Dr. Kim and Dr. Brewer has been profoundly rewarding. Each has taught me invaluable lessons about pushing boundaries, introducing new ideas, maintaining determination, guiding others toward shared goals, and embracing risk and uncertainty. Jim and Terry’s legacy is a profound reminder of what leading with purpose means. Their unwavering commitment to championing the well-being of employees, supporting their families, and uplifting communities reflects a vision of leadership that transcends business success. They have demonstrated that building a sustainable and inclusive future isn’t just an ideal but a responsibility. They have set a powerful example of how businesses can be a force for good, paving the way for a better world for all.
Finally, serving on the U.S. Department of Commerce Industrial Advisory Committee has been another career high point. This committee comprises leaders from academia, the semiconductor industry, federal laboratories, and other federal agencies, all working together to shape the future of microelectronics in the U.S. I am honored to contribute to such a critical mission for our nation’s technological advancement.
Throughout your career, what do you see as the most transformative change in packaging and test?
The core functions of the semiconductor package have remained consistent over the years, which provide for electrical connectivity, power and signal distribution, heat dissipation, protective covering, and facilitating chip handling. Yet, the diversity and complexity of package types has exploded in response to the growing demand for digital devices and the insatiable appetite for embedding increased functionality into these devices.
Over the past five decades, the landscape has shifted dramatically. As chips have become smaller, more powerful, and multifunctional, packaging and test processes have had to evolve to keep pace. This evolution has given rise to advanced packaging technologies, which require precision processes and capabilities far exceeding legacy or mainstream packaging solutions.
Advanced packaging has blurred the lines between front-end and back-end processes. Many manufacturing operations required for advanced packaging now resemble those used in wafer fabrication. This convergence underscores back-end operations’ increasing complexity and capital intensity, reshaping their role in the semiconductor manufacturing ecosystem.
In the early years, back-end packaging and test were relatively simple processes. They relied heavily on many lower-skilled factory workers and were far less capital-intensive than front-end wafer fabrication processes. Back-end services traditionally accounted for approximately 15% of the total packaged cost of an integrated circuit. In contrast, front-end processes require highly skilled scientists, engineers, and technical staff to operate expensive, sophisticated equipment in cleanroom environments, making front-end operations the focus of cost management, profitability, and free cash flow generation efforts. Management priorities naturally aligned with where most costs and revenue were concentrated—the front-end.
Advanced packaging enables the integration of multiple chips and components into highly integrated, multifunctional subsystems. These technologies support side-by-side placement of chips and chiplets using a silicon bridge or interposer (2.5D) or direct stacking without intermediary layers (3D), such as die-to-die, die-to-wafer, or wafer-to-wafer stacking. This approach allows for:
Legacy packaging, by contrast, remains focused on single-die or few-die configurations mounted to a laminate substrate. These packages use larger feature sizes and wire bond connections to interface with the external environment. These packages are inexpensive to produce with a proven track record of reliability.
The transformation of back-end packaging and test over the years highlights the industry’s adaptability to technological advancements and market demands. What was once a cost-efficient, labor-intensive segment has evolved into a critical, innovation-driven part of the semiconductor value chain. The convergence of front-end and back-end processes in advanced packaging underscores the growing importance of precision, integration, and performance, setting the stage for the next wave of semiconductor innovation.
Fig. 1: Intel’s view of packaging evolution and technology convergence is reflected in comparing legacy and advanced packaging. (Source: Intel)
Can you discuss how the convergence of front-end and back-end processes reshapes the semiconductor industry?
The convergence of front-end and back-end processes in semiconductor manufacturing is reshaping the industry, opening abundant opportunities across the value chain. As we move forward, integrating these traditionally separate domains promises to redefine what is possible in semiconductor design and manufacturing, paving the way for unprecedented advancements across various applications. Companies that embrace this paradigm shift, whether through strategic investments, innovative technologies, or collaborative alliances, are poised to lead the next era of semiconductor innovation.
Heterogeneous integration, combining diverse chiplets or components with different functionalities in a single package, drives the growing importance of advanced packaging techniques. The development of silicon interposers and bridges, along with novel interconnect methods, enables tighter coupling between components, driving breakthroughs in artificial intelligence (AI), high-performance computing (HPC) and the Internet of Things (IoT). This approach goes beyond traditional scaling to address challenges associated with Moore’s Law.
Leading players in the semiconductor industry are making substantial investments to capitalize on this convergence. Pure-play foundries, particularly TSMC, have taken a commanding lead in this space. TSMC’s strategic multi-billion-dollar investments in advanced packaging facilities in Taiwan underscore its commitment to this transformative shift. Through its 3DFabric system, which includes the SoIC series for stacking technologies, for chip-on-wafer-on-substrate (CoWoS) integration, and InFO fan-out packaging technologies, TSMC currently dominates advanced packaging manufacturing at scale globally.
Fig. 2: The new TSMC 3DFabric Alliance is TSMC’s sixth OIP Alliance and the first of its kind in the semiconductor industry that joins forces with partners to accelerate 3DIC ecosystem innovation and readiness, with a full spectrum of solutions and services for semiconductor design, memory modules, substrate technology, testing, manufacturing, and packaging. (Source: TSMC)
Advanced packaging technologies are also critical in producing high bandwidth memory (HBM) chips. HBM chips are foundational to modern AI systems’ performance and energy efficiency, enabling faster processing of complex models and large datasets. SK Hynix and Micron play a key role in this landscape, utilizing 3D stacking to vertically stack memory dies on top of each other and connect them with through-silicon vias (TSVs). TSVs are vertical electrical connections that run through the silicon dies, enabling fast and efficient communication between stacked memory layers. Micro-bumps connect the stacked dies within the HBM stack. The 3D stacking technology allows for high data density in a small physical footprint. These HBM packaging processes require front-end engineering and manufacturing capabilities. SK Hynix and Micron are adding manufacturing capacity to support the growing demand for AI systems and other data-intensive applications.
Chinese semiconductor companies are investing significantly in HBM packaging to build upon their capabilities to support the growing demands of AI and high-performance computing applications. Notable developments include:
These strategic investments underscore China’s commitment to strengthening its domestic advanced packaging capabilities and competitiveness in AI. The impact will depend on how the United States and other nations adapt to this evolving landscape.
China plays a pivotal role in both legacy and advanced packaging manufacturing. From a geopolitical perspective, the United States, China, and other nations could benefit significantly from adopting more forward-thinking and collaborative policies. Such policies can establish guardrails that balance protecting national security with promoting economic and scientific progress. Competition is a key driver of innovation.
Integrated Device Manufacturers (IDMs) are ramping up their back-end packaging efforts. For instance, Samsung Electronics has announced the development of 3.3D advanced packaging technologies aimed at artificial intelligence (AI) semiconductor chips. This involves innovative techniques like die stacking and silicon interconnect bridges, demonstrating Samsung’s intent to lead in advanced packaging for cutting-edge applications. Similarly, Intel’s 3D Foveros advanced packaging technology, now in production at its Fab 9 facility in New Mexico, USA, represents another significant milestone. Foveros enables vertical stacking of logic chips, paving the way for new levels of performance and efficiency.
Fig. 3: The CHIPS investment would turn Samsung’s existing presence in Texas into a comprehensive ecosystem for the development and production of leading-edge, current-generation, and mature node logic chips in the United States, including two new leading-edge logic fabs and research and development (R&D) in Taylor, as well as an expansion to the company’s existing Austin facility. It also demonstrates Samsung’s ongoing commitment to the United States, which has been manufacturing chips since 1996. (Source: Samsung)
Fig. 4: Intel’s opening Fab 9 in New Mexico will be instrumental in the industry’s high-volume 3D Foveros advanced packaging technology manufacturing. Fab 9 is part of Intel’s previously announced $3.5 billion investment to equip its New Mexico operations to manufacture advanced semiconductor packaging technologies. (Source: Intel)
Outsourced Semiconductor Assembly and Test (OSAT) providers are equally active in this transformative phase. Industry giants like Amkor and ASE are making significant investments to expand their capabilities in advanced packaging. These companies are enhancing their technological portfolios to meet the increasing demand for sophisticated packaging solutions.
Fig. 5: The image is a conceptual rendering of the Amkor fab that will be built in Arizona, providing 500,000 sq ft of clean room space to support the growth of advanced packaging in the USA. (Source: Amkor Technology)
Smaller OSATs are also finding new opportunities by engaging in collaborative alliances. These smaller entities can share resources and expertise by partnering with foundries, IDMs, and other ecosystem players, unlocking pathways to innovation and market competitiveness. Collaboration fosters a more integrated approach to manufacturing, enabling the development of novel packaging solutions that were previously unattainable.
The recent announcement of the Advanced Packaging Pilot Facility (PPF) at Arizona Research Park in Tempe, Arizona, under the U.S. Chips for America National Advanced Packaging Manufacturing Program (NAPMP) and Natcast, adds significant momentum to these collaborative efforts. This facility aims to provide a manufacturing-like environment for R&D, focusing on novel materials, device architectures, and advanced packaging processes. It will also serve as a hub for workforce development, offering hands-on research opportunities with cutting-edge tools and equipment. This initiative underscores the critical role of collaboration and innovation in driving advancements in semiconductor packaging and supporting the broader U.S. semiconductor ecosystem.
The federal government is home to many exceptionally talented packaging and test scientists and engineers who have historically been engaged by industry on an ad hoc, agency-specific basis. The CHIPS for America programs’ (CHIPS.gov) new emphasis on the whole-of-government approach creates a unified framework, enabling industry to tap into this vast reservoir of expertise more strategically. This alignment maximizes the collective potential of federal agencies like the National Institute of Standards and Technology (NIST) and National Labs. It brings tremendous leverage to the industry by fostering more seamless collaboration across all federal government agencies.
Fig. 6: the U.S. Department of Commerce and CHIPS for America program develops an ecosystem focused on technological development. (Source: National Institute of Standards and Technology)
In addition, US government-backed Manufacturing USA Institutes like AIM Photonics, NextFlex, and others are catalyzing innovation in photonic interconnects and flexible hybrid electronics. These institutes are exploring many new possible advanced packaging solutions:
As these trends accelerate, we may witness the emergence of entirely new processes that further blur the boundaries between front-end and back-end operations.
Fig. 7: Across the country, there are institutes focused on developing various areas of the advanced packaging industry for a collaborative effort to support the USA’s domestic production of advanced materials. (Source: NextFlex March 2022 presentation, slide 6: https://www.nextflex.us/wp-content/uploads/2022/03/PC-7.0-Proposers-Day.pdf)
Finally, the role of cloud hyperscalers, such as AWS, MSFT Azure, Google Cloud, Apple Cloud, IBM Cloud, and Alibaba, in the future of advanced packaging manufacturing is indeed a fascinating topic as it lies at the intersection of technology innovation, supply chain dynamics, and strategic business considerations.
Today, many hyperscalers rely heavily on third-party providers like TSMC for advanced packaging manufacturing. This relationship provides hyperscalers access to cutting-edge manufacturing capabilities but also makes them dependent on external supply chains, posing risks regarding capacity constraints, geopolitical tensions, and competitive priorities.
Hyperscalers could consider acquiring foundries or investing in back-end fabs to mitigate risks and gain control over their supply chains. Doing so would enable them to:
A more feasible approach might involve a hybrid model where hyperscalers collaborate with foundries like TSMC while selectively investing in niche advanced packaging manufacturing capabilities.
What are the biggest challenges facing semiconductor packaging and test today?
The challenges facing semiconductor packaging and test are significant, but I view them as opportunities for innovation and growth. With the right vision and determination, these challenges can inspire groundbreaking solutions.
In the U.S., some of the brightest minds from industry, academia, and government have conducted in-depth SWOT analyses of the difficulties and opportunities in advanced packaging. These efforts have resulted in invaluable reports offering insights and recommendations essential for anyone looking to identify and explore these opportunities further. The reports provide actionable solutions and strategies to address the many challenges.
Here are some of the most notable reports:
Additional white paper reports and funding opportunities for Advanced Packaging R&D initiatives are available on the CHIPS.gov website, managed by the U.S. CHIPS for America Programs under NIST.
These resources are a treasure trove for those ready to embrace the challenges in this field as opportunities for exploration and innovation.
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