Physical effects will become a major issue for stacked die; power is at the top of the list.
There’s a great and often over-used line out of movie scripts when the hero stumbles upon something that doesn’t make sense and he’s told, “That’s on a need-to-know basis.”
The same seems to be true in low-power engineering. While everyone talks about the need for reducing the power inside of chips, the reality is that only the really advanced SoC and processor companies are taking it seriously. For most other companies, advanced nodes provide plenty of real estate for limiting proximity effects—particularly if there are enough sectors that are in the off state most of the time and there aren’t anywhere near the 100 million gates being packed into smart phone chips.
In any case, there’s always the process technology to bail them out. Low-power processes can and flows can, in fact, save many designs. That will end in 2.5D stacks, which many companies have been advocating as a way of avoiding the headaches of developing new analog IP at each new process node. While they will save NRE costs on the analog side, the physical effects of power will become much more pronounced.
By most accounts we are still at least a year away from commercial introduction of stacked die, and for many companies at least two years. But when the chip market does shift, it will do so with a vengeance and power will be one of the key issues that must be dealt with from the start. For anyone who’s been giving power only passing notice, it’s time to break out the technical papers and start brushing up on these issues. Power isn’t going away, but the jobs of people who don’t recognize its importance could well disappear.
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