Best Practices For Power-Aware Verification: Because Designing For Low Power Is Only Half The Battle

As modern chips push the limits of power efficiency, power management has become a top priority. With today’s increasingly complex devices, verifying power intent isn’t just a technical requirement. It’s a necessity for building reliable silicon.

One of the most important lessons learned in recent years is that RTL and power intent must evolve together. Treating power intent as a post-RTL task almost always causes trouble. Hierarchies drift, domains fall out of sync, and critical strategies like isolation and retention can easily break. The more effective approach is to build the power intent in parallel with RTL development. A few examples include updating the Unified Power Format (UPF) spec as modules change, interfaces shift, and the design grows.

But even with synchronized RTL and UPF efforts, verification remains a serious challenge. That’s where a multi-layered verification strategy comes in. Static checks help catch structural issues early. This includes things like mismatched domains or missing supply nets. But structure alone isn’t enough. You also need dynamic simulation to see how the design behaves over time. Verifying transitions, retention restores, and isolation during real operation are examples of such tasks.

Fig. 1: Integrated functional and low power simulation with Questa One Sim Power Aware.

Regression testing also needs an upgrade. If you’re only running traditional functional tests, you’re probably missing a whole class of bugs tied to power transitions. Power-aware test cases that toggle isolation logic, cycle domains, and exercise save/restore paths, etc., should be a standard part of your regression suite. These aren’t corner cases anymore. They’re core to how chips operate today.

And let’s not forget the human side of the process: cross-team collaboration is crucial. Power intent affects RTL coding, verification, implementation, and synthesis. Misalignment across any of those teams can lead to nasty surprises late in the game. Regular reviews, shared signoff criteria, and clear communication help everyone stay aligned and reduce the risk of expensive rework.

In short, getting power-aware design right takes discipline. It’s not just about using the right tools. It’s about putting the right processes in place early and sticking to them. That means building power intent alongside RTL, verifying it at every layer, tracking meaningful coverage metrics, and ensuring every team is part of the loop.

Closing the loop on power intent verification

To help teams address these challenges at the signoff level, Questa One Sim Power Aware provides a purpose-built framework for verifying that UPF-based power intent is not only defined correctly but is also functionally validated against RTL behavior. It detects mismatches, verifies correct behavior across domain transitions, and ensures alignment between power definitions and synthesized logic. By integrating static and dynamic checks into a cohesive flow, Questa One helps teams achieve signoff confidence much earlier in the development process.

For a deeper dive into how Questa One supports structured power-aware verification, check out the white paper on power intent signoff best practices, A guide to UPF-based power intent verification with Questa One.