Blog Review: April 29

NPU simulator; the many tools of verification; formal exposure.


Arm’s Paul Whatmough checks out SCALE-Sim, an open source cycle-accurate simulator specifically for neural processing unit (NPU) architectures.

Mentor’s Neil Johnson shows how a complete verification methodology requires complementary deployment of multiple techniques, with different options at each level of abstraction.

Cadence’s Paul McLellan checks out challenges in automotive reliability, FIT rates, and the role of transistor aging and early life failure.

Synopsys’ Sean Safarpour takes a formal approach to calculating potential virus exposure and how it fits with different ways of assessing the reachability problem in verification.

Ansys’ Craig Hillman and Theresa Duncan explain why material characterization is an important part of electronic simulation and why data sheets alone may not have all the needed information.

Silicon Labs’ Kevin Smith digs into how to identify and address parasitic PLLs with a detailed look at measuring injection sensitivity and to do with that information.

In a blog for SEMI, Walt Custer of Custer Consulting considers the economic impact of Covid-19 through the lens of manufacturing activity in China and Taiwan and early indicators in wafer foundry results.

Intel’s Carlos Cordeiro takes a look at the FCC’s recent ruling to permit unlicensed Wi-Fi devices access to additional spectrum in the 6GHz band and what it means for consumers.

Similarly, NXP’s Mark Montierth points out how opening the continuous 1200 MHz swath for new Wi-Fi 6E devices will mean less congestion in areas with many legacy networks.

And don’t miss the blogs featured in last week’s Systems & Design newsletter:

Editor in Chief Ed Sperling explains why planar scaling is running out of steam, even if it’s technologically possible.

Mentor’s Jean-Marie Brunet warns that the number of tests required to verify 5G networking SoCs is growing tremendously.

Synopsys‘s Dave Reed contends that on their own, better tools aren’t enough to keep pace with analog design challenges.

Aldec’s Farhad Fallahlalehzari digs into the technical challenges that persist in developing systems to process 4K Ultra HD resolution data.

Cadence’s Frank Schirrmeister sheds light on what the universal language means to the development of electronic systems.

Vtool’s Hagai Arbel asks, ‘Why the heck did it take me three days to find this bug?’

Codasip’s Roddy Urquhart elucidates why even if the RTL and a toolchain are available for free, there are plenty of costs associated with using an open source core in an IC design.

Imagination Technologies’ Gerry Conlon describes how the rapidly growing connected IoT market offers ideal conditions for dynamic companies to quickly gain market share.

OneSpin Solutions’ Rob van Blommestein opens the doors on a weekly scavenger hunt and other educational opportunities.

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