Speed; cheap light; wall smashing; MEMS sensors; backward compatibility; DDR’s future; batteries.
By Ed Sperling
Synopsys’ Eric Huang unveils the fastest USB ever. The seat belt is extra.
Mentor’s Nazita Saye sees the light—well, at least a refracted version of it—through the lens of a plastic bottle. This one is a real energy saver for the money, even if you have to forfeit the recycling fee. Check out the link.
Cadence’s Brian Fuller takes a sledgehammer to the semiconductor memory wall, only to find there’s a CPU wall behind it. This is like finding out there were two Berlin Walls. The good news is there are still some tunnels.
Semico Research’s Tony Massimini predicts that MEMS sensors and actuators will become a staple for the Internet of Things. The ramp-up forecasts are well into the double digits.
Synopsys’ Richard Solomon looks at the fallout of the old SATA standards versus the new one that connects to PCIe. The trouble is that with backward compatibility, many vendors have to support both.
Mentor’s Harry Foster introduces part nine of his epic functional verification study. The subject for this week: testbench methodology and class library adoption.
Cadence’s Richard Goering looks at competing memory standards, which were discussed at a Memcon panel. The surprise is that DDRx is the default winner—at least for now.
Mentor’s Colin Walls looks at future battery and memory technology—and the dearth of information about resistive RAM as a flash replacement.
Synopsys’ Mick Posner uncorks his latest installment on hybrid prototyping. One size does not fit all.
Suppliers are investing new 300mm capacity, but it’s probably not enough. And despite burgeoning 200mm demand, only Okmetic and new players in China are adding capacity.
Different interconnect standards and packaging options being readied for mass chiplet adoption.
Continued expansion in new and existing markets points to massive and sustained growth.
Aging equipment and rising demand are pushing up prices and slowing production.
Experts at the Table: Designing for context, and geopolitical impacts on a global supply chain.
Interest in this particular ISA is expanding, but the growth of other open-source hardware is less certain.
Nanosheets are likeliest option throughout this decade, with CFETs and other exotic structures possible after that.
Hybrid bonding opens up whole new level of performance in packaging, but it’s not the only improvement.
Why this is becoming a bigger issue, and what can be done to mitigate the effects.
Suppliers are investing new 300mm capacity, but it’s probably not enough. And despite burgeoning 200mm demand, only Okmetic and new players in China are adding capacity.
From low resistance vias to buried power rails, it takes multiple strategies to usher in 2nm chips.
Manufacturing 3D structures will require atomic-level control of what’s removed and what stays on a wafer.
Disaggregation and the wind-down of Moore’s Law have changed everything.
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