Blog Review: Aug. 29

Mentor’s Joe Hupcey III addresses inconclusive results in formal verification with tips on how to reduce the complexity of “assumption” properties to make them easier for the formal engines to digest and reach a solution.

Cadence’s Meera Collier looks beyond the immediate appeal of autonomous cars to the broader social implications of urban sprawl, public transit funding, and gentrification.

Synopsys’ Haidee LeClair points out a new security problem for Philips’ medical data management products that could allow access to cardiac patient data, but notes that while the vulnerability is troubling, it’s an example of security discloses done right.

In a video, VLSI Research’s Dan Hutcheson chats with Mentor’s Wally Rhines about a new wave of growth for the semiconductor industry and the major impact of China’s fabless companies.

SEMI’s Serena Brischetto chats with Xperi’s Petronel Bigioi about infrastructure changes needed to implement deep learning and the problems with storing a network in memory without encryption.

Arm’s Jason Andrews provides a tutorial on using code coverage with the Cortex-M3 DesignStart eval package to ensure embedded software is fully exercised and tested.

A Rambus writer points to signs that memory prices may soon fall, thanks to a combination of new fabs and lower cryptocurrency values.

Nvidia’s Isha Salian looks at a new method to improve natural language processing by using a language model that can account for one word having multiple meanings.

Plus, check out the blogs featured in last week’s System-Level Design newsletter:

Editor in Chief Ed Sperling points to multiple levels of innovation plus AI in new chips.

Technology Editor Brian Bailey goes deep undercover to ask when removing someone from a project actually improves it.

Mentor’s Matthew Knowles contends that the process of test pattern bring-up, debug and device characterization is ripe for improvement.

OneSpin’s Sergio Marchese argues that engineers developing automotive chips need clear information, but some EDA vendors are muddying the waters.

Cadence’s Frank Schirrmeister points to 5G devices, low power, system of systems, and architecture/performance as the key verification drivers.

Synopsys’ Bernadette Mortell observes that the complex process and layout rules for finFET processes have a big impact on decisions made during synthesis.

Aldec’s Sunil Sahoo explains how to directly access registers by name from the testbench, without having to know where and what they are.