Blog Review: Aug. 30

ML and chatbots; IoT legislation; virtual fabrication & assembly data; new wave of verification; memory in the data center.


Cadence’s Meera Collier explains machine learning, unsupervised algorithms, and why Facebook’s recently publicized AI chatbot conversation isn’t as inscrutable as it sounds.

Synopsys’ Robert Vamosi considers recently proposed legislation which seeks to mitigate the risk of botnets commandeering IoT devices used in the U.S. government, including limiting the use of hard-coded passwords and certifying there are no known security defects.

Mentor’s Ryan Kasnick points to the importance of accurate fabrication and assembly data and how virtual documentation can help.

Lam’s Tim Archer and Rick Gottscho chat about the challenges and opportunities for 3D NAND, the 3D evolution of memory and logic, and the enabling roles that storage and memory play.

Verification blogger Gaurav Jalan chats with DVCon India keynote speaker Ravi Subramanian on how the convergence of different technologies is changing verification and what the EDA industry is doing about it.

Rambus’ Aharon Etengoff points to a discussion on how new memory technology, including DDR4 and HBM, can help bolster both bandwidth and capacity in the data center.

In a two-part blog, Intel’s Jakob Engblom explains the ‘small batches principle’ of development, how it’s useful for hardware, and how to implement it with agile and simulation.

Applied’s David Britz argues for the value of cross-industry cooperation in developing new materials and processes, with ceramic thermal spray coating technology as an example.

Arm’s Julio Suarez digs into improving cloud management tool deployments on Arm and other non-x86 architectures using Weavesocks.

Synopsys’ Iain Singleton points out how often our brains use abstractions without us thinking about it, and how that applies to formal.

What is the current state of the Chinese semiconductor industry? Cadence’s Paul McLellan listens in on four perspectives from SEMICON.

And don’t miss the blogs featured in last week’s System-Level Design newsletter:

Editor In Chief Ed Sperling explains why China’s new policy may have big implications for semiconductors and IP.

Mentor’s Craig Armenti contends that multi-board design and cross-domain communication are no longer optional.

OneSpin Solutions’ Dave Kelf predicts that advances made for automotive electronics will make their way into many other sectors.

eSilicon’s Mike Gianfagna observes that for leading-edge designs, success can depend on how a team is trained.

Aldec’s Janusz Kitel finds that good management of traceability data can prevent specification errors and save time.

Cadence’s Frank Schirrmeister examines some fascinating but disturbing advances in technology.

ARM’s Jason Andrews digs deep into how to identify and eliminate software bottlenecks.

Technical Editor Brian Bailey points out that to innovate, you have to see patterns from the past and project them into the future.

Synopsys’ Malte Doerper reminds why it’s so important to keep track of system requirements throughout the design process.

ArterisIP’s Kurt Shuler discusses the fact that the real value in planning interconnects may not be obvious until after the chip is taped out.

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