Blog Review: Feb. 6

Verification time; emerging memories; secure processors.


Mentor’s Harry Foster examines the impact of growing design complexity on how long designs spend in verification, the ratio of design to verification engineers on a project, and how they spend their time.

Cadence’s Paul McLellan checks out some of the emerging memory technologies and notes there’s no clear indication which will dominate the market.

Synopsys’ Meenakshy Ramachandran checks out the new version of high dynamic range, Dynamic HDR, supported by HDMI 2.1 and how it works to reproduce every frame as close as possible to the original image.

One year after the disclosure of Meltdown and Spectre, Rambus’ Paul Kocher considers the tradeoffs of performance and safety and why the focus on processors tailored for security is encouraging.

Applied Materials’ Sanjay Natarajan argues that AI can be a vital disrupter of the semiconductor industry’s continual improvement mindset.

Intel’s Ron Wilson digs into the major efforts to fit machine learning into the edge environment by improving accuracy, reducing the size of models with compression, and adding hardware accelerator chips.

Arm’s Robert Day points to a number of challenges autonomous vehicles face on the road to large scale deployment, from high price to increased software complexity.

NI’s James Kimery takes a look at architectural choices in deploying mmWave 5G.

Plus, don’t miss the blogs featured in last week’s System-Level Design newsletter:

Editor In Chief Ed Sperling examines the impact of rapid technology changes and uncertain interactions.

Technology Editor Brian Bailey wonders if too much AI is a good thing.

Cadence’s Frank Schirrmeister asks how much further left can we shift.

OneSpin Solutions’ Tom Anderson says formal apps can target specific verification problems at a full-chip level, even on very large designs.

Synopsys’s Jim McCanny warns that an often-overlooked cause of hold violations no longer can be ignored.

Mentor’s Jean-Marie Brunet explains why determinism, scalability and virtualization are all vital to AI verification.

eSilicon’s Mike Gianfagna reminds us that while a chip may work, it’s only successful if it performs in the context of the delivered system.

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