Blog Review: Jan. 17

CXL and cache coherence; protecting DRAM; parasitic extraction and 3D-IC.


Cadence’s Rajneesh Chauhan introduces the Back-Invalidate feature in Compute Express Link (CXL) 3.0 and how it contributes to the efficient functioning of modern data center architectures by upholding cache coherence across multiple hosts and devices.

Synopsys’ Brett Murdock and Dana Neustadter point out the importance of protecting against DRAM attacks such as Rowhammer, RAMbleed, and cold-boot attacks to keep bad actors from reading or corrupting data, or from retrieving cryptographic keys which are fundamental to security, and suggest some strategies for securing DDR/LPDDR interfaces.

Siemens’ John McMillan finds that new parasitic extraction technologies are necessary to ensure accurate capture of parasitic and layout-dependent effects for non-planar devices and emerging 3D-IC designs.

Ansys’ Kim Woodham and Laura Carter look at trends shaping the automotive industry, from electrification and autonomous vehicles to connectivity and AI.

Arm’s Oscar Zhang introduces a system tracing tool to enable users to collect performance information from Android Debug Bridge, do system profiling, and record system tracing to help analyze and debug graphic issues.

Keysight’s Anna McCowan considers the risks and benefits of incorporating AI in software test automation, such as the ability to test for things previously thought subjective.

SEMI’s Ming-Chang Wu highlights cooperation between Taiwan and the U.S. on cybersecurity standards for the semiconductor industry and Taiwan’s key role in helping ensure supply chain resiliency.

Plus, check out the blogs featured in the latest Low Power-High Performance newsletter:

Quadric’s Steve Roddy finds that many already are predicting the end of an AI era that just began.

Keysight’s Jenn Mullen looks at overcoming test automation debt and improving productivity for QA engineers and software developers.

Rambus’ Tim Messegee digs into how a memory interface chipset can boost bandwidth.

Arm’s Brian Jeff offers techniques on using a hardware-assisted CPU profiling mechanism for source code hotspot detection, memory access analysis, and data sharing issues.

Cadence’s Louis Tsai shows how to manage and mitigate heat-related issues to preserve longevity and reliability.

Ansys’ Tobias Lauinger explains how to avoid unwanted scattered or specular light at the smartphone camera sensor with simulation.

Synopsys’ Andrew Appleby, Xiaorui Hu, and Bhavana Chaurasia lay out how specially architected logic cells and memory cache instances help meet design goals.

Siemens EDA’s Janet Attar presents a way to create a high-quality floorplan in a fraction of the time.

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