Blog Review: Jan. 2

Cadence’s Paul McLellan listens in as Uhnder CEO Manju Hegde explains the most critical issues impacting sensor development for autonomous vehicles and why new radar systems are needed to fill in the gaps.

Synopsys’ Fred Bals shares key points from the U.S. House Oversight and Government Reform Committee’s investigation into the massive Equifax data breach that show how relatively small security missteps can cascade.

Mentor’s Simon Favre argues that critical area analysis is vital in improving manufacturability of ICs.

Applied Materials’ Sanjay Natarajan considers what may come in the next 25 years of electronics development, from a revolution in EDA to increases in efficiency making energy harvesting feasible.

GlobalFoundries’ Thomas Caulfield argues that there are many ways to achieve the net effect of Moore’s Law that don’t require billions of dollars in annual R&D and capital expenditures.

ANSYS’ Robert Harwood looks at why the IoT is a key enabler for autonomous cars and vehicle electrification.

Arm’s Hannes Tschofenig checks out testing performance and power consumption of typically-used cryptographic functions using the SecureMark-TLS benchmark.

Silicon Labs’ Kevin Smith digs into how to calculate the total jitter for a noisy source clock tree that includes a jitter attenuator.

Eindhoven University of Technology’s Adrie Mackus explains the development of area-selective atomic level deposition and how it’s been pushed by self-aligned fabrication.

Inficon’s John Behnke argues that 300mm fabs could be a lot smarter with the use of digital twins to help optimize future actions.

UltraSoC’s Andy Gothard observes that RISC-V is maturing and the ecosystem is growing quickly with major players investing in the ISA.

And don’t miss the blogs highlighted in the latest System-Level Design newsletter:

Editor in Chief Ed Sperling digs into massive changes across the semiconductor industry.

Technology Editor Brian Bailey looks at which articles were the most popular over the past year and where the surprises were.

Mentor’s Yousry ElMaghraby compares parasitic effects using two different methods.

UltraSoC’s Gajinder Panesar contends that designing an SoC is no longer just about the processor.

Cadence’s Frank Schirrmeister points to the next drivers of verification productivity growth.

Aldec’s Farhad Fallahlalehzari argues that while GPUs are well-positioned in machine learning, data type flexibility and power efficiency are making FPGAs increasingly attractive.

Synopsys’ Mike Thompson shows how controllers enable new SSD features.

OneSpin’s Sergio Marchese uncorks a design and formal verification holiday puzzle that involves flowers, leaves, branches, and even bees.