Blog Review: July 30

Mentor’s Colin Walls looks at a free collaborative online tool called codepad, which can be used for compiling, interpreting and executing code quickly. Free is good—sometimes.

Cadence’s Brian Fuller followed a recent panel on high-speed, cross-fabric interface design, which focused on why designers need to consider chip, package and board to ensure signal and power integrity. So what really happens when digital becomes more like analog?

Synopsys’ Karen Bartleson digs into the subject of standards and patents—and the often ugly times when they overlap. IEEE is in the process of updating its patent policy.

Ansys’ Bill Vandermark looks at the top five engineering technology articles for the week. Check out the one on spacesuit technology showing up in high-end dress shirts to reduce sweat, and another on smarter seatbelts that can wake you up when you’re too relaxed.

Carbon Design Systems’ Jason Andrews looks at the migration path to ARM’s new 64-bit software and how to use the new compiler technology.

The F-35 Joint Strike Fighter fleet has been grounded. Mentor’s J VanDomelen talks about what went wrong.

Cadence’s Richard Goering analyzes a presentation by Broadcom principal engineer Harshat Pant on static low-power verification and how to get the most out of it. The biggest challenge: Preparing the “golden CPF” file.

ARM’s Ellie Stone gives a run down on everything from graphics to quarterly numbers and democratizing technology.

What do roadrunners and FPGA prototypes have in common? If you answered feathers, you’re wrong. Speed is correct. Synopsys’ Mick Posner sheds some light on accelerating time to first prototype and the California earth-cuckoo.

Mentor’s Nazita Saye pitches the upside of simulation, but to the wrong crowd.

And in case you missed last week’s System-Level Design newsletter, here are some noteworthy blogs:

Arteris’ Kurt Shuler looks at the battle brewing in your garage and on the road between Apple CarPlay and Android Auto.

Open-Silicon’s Jeff Scott points to the benefits of fully functional virtual prototypes of complex multicore SoCs.

eSilicon’s Mike Gianfagna notes that all the work that’s been done in getting ready for stacked die could pay big dividends soon.

Synapse’s Satish Bgalkotkar contends that the industry needs to take a step back and think about where we’re heading.

Synopsys’ Tom de Schutter finds analogies on his road trip through Yellowstone National Park to virtual prototyping.

Cadence’s Frank Schirrmeister finds engineering teams are using a continuum of development engines.

And Technology Editor Brian Bailey discovers a neglected patent that merged East and West.