Blog Review: July 31

Cadence’s Jasmine Makhija explains how to boost the performance of CXL 3.0 by using NOP (No Operation) Insertion Hints in latency-optimized 256B Flit Mode, which enables the system to quickly revert to the low-latency path after temporarily switching to a higher-latency path due to error correction needs.

Synopsys’ Robert Fey finds that by automatically and dynamically linking requirements and test cases, the software testing process becomes significantly more efficient and precise by reducing manual effort and improving fault analysis.

Siemens’ Francisco Ezquerra Larrodé introduces a comprehensive, open-access computational fluid dynamics training course that combines theoretical lectures, worked examples, and hands-on simulations.

Keysight’s Ben Miller explains how CXL enables data center fabrics comprised of interoperable elements to share resources and tackle tough computational problems, like processing the petabytes of data necessary for AI, ML, edge computing.

Arm’s Chloe Ma suggests that a combination of hardware advancements, model optimization techniques, and new software solutions will be needed to overcome the resource constraints and enable the potential of multimodal AI and computer vision at the edge.

Infineon’s Rick Schneider shows how to manage the flash memory of Bluetooth devices and segregate the application storage needs from other long-term storage needs so that important data can be remembered by the device across reboots and reprogramming.

Renesas’ Jacob Reyes considers some of the unique requirements and design challenges of smart rings, such as form factor, robustness, visual appeal, comfort, and battery runtime.

Ansys’ Aliyah Mallak checks out the impact clothing and hairstyles have on the performance of an athlete’s flight during the long jump event using computational fluid dynamics.

SEMI’s John Cooney listens in as Laurie E. Locascio, U.S. Under Secretary of Commerce for Standards and Technology, provides an update on the implementation of the CHIPS Act and future plans, including significant investment in advanced packaging.

Plus, check out the blogs featured in the latest Low Power-High Performance, Manufacturing, Packaging & Materials, and Systems & Design newsletters:

Technology Editor Brian Bailey explains how companies are harvesting expertise from their senior engineers and making it available to new hires and junior engineers.

Movellus’ Aakash Jani and Lee Vick show why SDC challenges require a multi-faceted approach involving advanced silicon lifecycle analytics and on-die telemetry.

Siemens EDA’s Michael Walsh, Jin Hou, and Todd Burkholder introduce a new way to functionally verify packaging connectivity using formal verification.

Synopsys’ Eldon Nelson digs into IDEs and how they help address a range of coding challenges, particularly with HDLs like SystemVerilog and VHDL.

Axiomise’s Ashish Darbari, Fabiana Muto, and Nicky Khodadad report on the good, bad, and unknowns of AI, and what’s missing for design and verification.

Keysight’s Roberto Piacentini Filho delves into IP catalogs and how they can break down silos by offering centralized repositories and fostering easy collaboration.

Cadence’s Rich Chang outlines common debugging issues with solutions to streamline the process and create efficient testbenches for hardware verification.

Arteris’ Ashley Stevens discusses the benefits of partitioning the system into shared and non-shared data regions with the shared data routing through a coherent interconnect.

Lam Research’s QingPeng Wang discusses the optimal way to perform deposition/etch cycling and improve critical dimension uniformity.

Amkor’s Heejun Jang shows how an extended platform of 2.5D Si interposer can break through the limitations of the large Si interposer fabrication.

Synopsys’ Wolfgang Demmerle explains why using contours is an effective way to extract all information within a SEM image’s FOV.

D2S/eBeam Initiative’s Asmus Hetzel talks about key trends at EMLC, including curvilinear design, AI in inspection, and multi-beam mask writers.

SEMI’s Krish Raghunath notes that wrap-around services, such as childcare and transportation, can help get under-represented communities into industry careers.

Synopsys’ Priyank Shukla presents a comprehensive analysis of 224Gbps PHY 3nm silicon results and their significance in the context of high-performance compute disaggregation.

Siemens EDA’s Gregory Beers emphasizes the value of flex-specific rules, and communication with fabs about multi-zone stack-up details.

Fraunhofer IIS/EAS’ Ron Martin provides a qualitative comparison of different sensor performance indicators.

Rambus’ Lou Ternullo digs into PCIe 7.0 and what’s new, including a 2X faster data rate and an optical interconnect option.

Cadence’s Geeta Arora delves into the semantics of PCIe 6.0 ATS request-completion protocol and invalidation protocol.

Arm’s Marcus Corbin explains how a DNN-based system can recognize a person based on the characteristics of their speech, with detailed findings from a research project.

Ansys’ Kiyoung Jung and KAIST’s Kyutae Kim show why the large-scale adoption of hydrogen as a cleaner fuel depends on solving issues related to flashback, NOx emission, and combustion instabilities.

Power architect Barry Pangrle examines the roadmap to increase the manufacturing competitiveness of the U.S. semiconductor industry.

Quadric’s Steve Roddy shows a graph compiler that enables rapid support for emerging AI models.