Blog Review: June 2

Synopsys’ Mike Borza checks out how automotive ECUs, infotainment systems, and in-vehicle networks can be compromised by attackers and why it’s important to follow cybersecurity best practices and keep security in mind starting early in the design cycle.

Cadence’s Paul McLellan checks out the results from the latest MLPerf benchmarks for machine learning inference systems, with the new inclusion of factoring in energy efficiency.

Siemens EDA’s Neil Johnson checks out some different ways to optimize build flows for simulation, from a simple lump sum build to options that enable an optimal SoC build flow.

In a podcast, Arm’s Geof Wheelwright chats with Dennis Laudick about the current trends around AI, efforts to make AI deployment easier for engineers and developers, and the importance of energy efficiency through algorithm and processing optimization.

In a blog for Ansys, Nicolas Riviere of Motor Design Ltd. Shares some of the complexities involved in designing electric motors and how multiphysics analysis aids in optimization.

The ESD Alliance’s Bob Smith chats with Adnan Hamid of Breker about why verification continues to take so much time, the shift-left trend, and additional challenges in verifying AI/ML applications.

Nvidia’s John Ashley breaks down the tools and techniques used to create explainable AI, which aims to provide a better understanding of how AI models come to their decisions.

And don’t miss the blogs featured in the latest Systems & Design newsletter:

Technology Editor Brian Bailey observes that change sometimes cannot be quantified enough to make a decision.

Synopsys’ Rahul Singhal explains why the size of massive, highly parallel AI processor chips has a significant impact on design and test methodologies.

Cadence’s Frank Schirrmeister examines how to balance of performance and power consumption at each level of the edge.

Codasip’s Roddy Urquhart finds that semiconductor scaling has fundamentally changed, with increasing specialization necessary to achieve performance gains.

Vtool’s Hagai Arbel contends that while the fundamentals of good engineering remain the same, it’s worth trying new ways of approaching a problem.

Siemens EDA’s Srinivas Velivala advises iterating through signoff-quality DRC in the implementation environment to reduce inefficiencies.

Calibra’s Jan Willis considers using GPUs as an enabler for curvilinear inverse lithography technology, and other ways to produce mask shapes in acceptable runtimes.