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Signoff DRC In P&R Lets You Get Better Products To Market Faster

Iterate through signoff-quality DRC in the implementation environment to reduce inefficiencies.

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Trust is generally a reflection of quality. You trust someone, be it an individual or a company, because they have, over time, consistently performed high-quality work. You trust a product because your past experience with that product has been positive, or the experiences of lots of other people have been positive. With that said, quality comes in shades and percentages. Most of us will happily buy an inexpensive pair of beach sandals when we’re on vacation for a week, but willingly spend more for a well-made, sturdy pair of shoes for year-round wear.

When it comes to integrated circuit (IC) design verification, the same principle holds true. A foundry’s design rules, encapsulated in a foundry-qualified design rule checking (DRC) rule deck, represent the ultimate level of quality for an IC design implementation. A “DRC-clean” design layout is the final deliverable in the IC design and verification flow. Foundries trust that a design that has passed verification against a foundry-qualified rule deck is ready for manufacture.

But you don’t always need the highest level of quality, right? Digital designers use place and route (P&R) tools to implement a physical construction of their IC designs. During digital design implementation, DRC functionality built into the place and route (P&R) tool is used to fix DRC violations in the layout. This native P&R DRC verification works well to resolve the majority of DRC errors, but it doesn’t (and isn’t intended to) completely and accurately reflect the full signoff DRC—it’s only a “first-pass” basic level of DRC verification to check the automated layout generated by the P&R tool.

But there are some categories of errors that this P&R DRC simply isn’t equipped to handle, the type that usually require many manual debugging and DRC iterations to fix, such as:

  • automated design enhancements that can create complex chip-level DRC errors
  • “last mile” functional and timing changes that result in new DRC errors
  • manual DRC error fixes made by the design team

For these sorts of errors, designers need to switch from their beach sandals to their sturdy shoes, the signoff DRC deck. That means merging the P&R data with IP data, streaming out the database to a GDSII/OASIS database, running batch DRC with a signoff rule deck, debugging and fixing the errors, then repeating the whole process again and again until the layout is clean. Each iteration usually takes hours to days, time that comes at the expense of the schedule and a company’s resources.

What if you could switch back and forth between your sandals and shoes at a moment’s notice? What if designers could use the built-in P&R DRC until they needed signoff-quality DRC verification, then invoke that signoff-quality DRC right there in the P&R tool? That’s the idea behind innovative EDA functionality that provides access to real-time signoff-quality DRC during P&R. Let’s take a look at how it’s implemented, using the Calibre RealTime Digital interface from Siemens EDA.

Calibre RealTime Digital provides direct calls to Calibre analysis engines running foundry-qualified signoff Calibre rule decks (figure 1). These engines perform fast, incremental checking near shapes being edited, providing nearly instantaneous feedback on DRC violations. Because the Calibre RealTime Digital interface is integrated with all major P&R tools, P&R engineers can get signoff-quality DRC results without leaving their P&R environment.


Fig. 1: The interface is integrated into all major P&R tools.

For example, fixing interface DRC errors between top-level and hierarchical blocks is typically a very iterative and time-consuming process. The Calibre RealTime Digital interface can intelligently merge only the required shapes from top-level and hierarchical blocks, launch a DRC run, and highlight both the DRC error marker and the IP shapes around the error marker in the P&R tool. Designers can now validate these interface DRC fixes without leaving the P&R environment (figure 2). Also, because most Calibre RealTime Digital iterations only take a few seconds to minutes to complete, compared to the typical 20+ hours for a full batch verification run, teams can shave days, even weeks, off their tapeout schedules.


Fig. 2: The flow enables multiple, fast DRC fix-verify iterations in the P&R environment.

In addition to just speeding up overall schedules, there are some other significant benefits to having that extra time. Calibre Realtime Digital can perform all the checks that can be run with the Calibre nmDRC platform, including recommended rules, pattern matching, equation-based DRC, preferred metal direction rules, and multi-patterning. That capability means digital designers can use some of their now-free time to run multiple “what-if” analyses on design rule violations and recommended rule compliance right there in their place and route (P&R) tools. The time and ability to run and compare several options lets designers focus more of their dedicated verification time and effort on optimizing a layout to achieve the design’s power, performance, and area (PPA) goals.

Designers implementing a design in a new design node must often spend some considerable time reading and deciphering complex design rules that have been added to the rule deck. With real-time DRC, they can simply apply the rules to the layout, iterate a few different options with the Calibre RealTime Digital interface, and get a quick understanding of how the parameters and application of that rule affect a design, and which layout options might work best. This ability to quickly understand and apply the design rules for a new process node can help a design company get their products to market sooner, which can result in a significant competitive advantage.

Especially at advanced nodes, eliminating inefficiencies and minimizing time- and resource-intensive activities can help improve market position and profitability. Giving design teams the option to use signoff-quality DRC in the P&R environment gives them more control over both the process and the results. By eliminating the gaps between the P&R tool’s built-in design rules and the foundry-qualified Calibre rule deck, P&R engineers now have access to accurate, up-to-date foundry information at the best possible time—while they are performing manual DRC error fixing during floorplanning and/or tapeout. In addition, design teams can spread out the use of both engineering and computing resources, reducing or eliminating the logjams incurred near the end of the tapeout cycle.

Beach sandals or sturdy shoes? Both have their uses, depending on the level of quality and trust you need. The ability to iterate through signoff-quality DRC in the implementation environment when needed enables P&R engineers to trust not only that their layouts are resistant to manufacturing variability issues and optimized for the most desirable performance and operational characteristics, but also that they can produce those layouts while minimizing resource usage and still meeting ever-tighter tapeout schedules.

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