Blog Review: June 23

Synopsys’ Manuel Mota shows how splitting SoCs into smaller dies for advanced packaging and using die-to-die interfaces to enable high bandwidth, low latency, and low power connectivity can benefit hyperscale data centers.

Siemens EDA’s Chris Spear explains the relationship between classes and objects in SystemVerilog with a handy visualization and notes the difference between SystemVerilog variables and class variables.

Cadence’s Paul McLellan listens in as Waylon Grange of Stage 2 Security demonstrates hacking the embedded software in a home’s solar power controller and how it points to areas where embedded security still needs improvement.

In a blog for Arm, Alp Acar of Boston University explains the concept of federated learning, a privacy-preserving paradigm to train machine learning models in a decentralized fashion, leaving a user’s data on the device.

In a video, Infineon’s Thomas Aichinger dives into how to make the gate oxide of SiC MOSFETs more reliable in the field through voltage screening and marathon stress tests.

Coventor’s Gerold Schropfer considers why it’s difficult to develop RF MEMS switches and some ways to optimize them and the surrounding system.

Ansys’ Susan Coleman checks out how simulation was used in the design of a four-wheel, encapsulated electric bike to balance aerodynamics, cost, and safety.

A Rambus writer discusses the company’s Compute Express Link initiative to enable memory expansion and memory pooling for improved data center architectures.

SEMI’s Rene Krantz points to a new collaboration with the U.S. Air Force Research Laboratory to match researchers with industry partners on smart medtech projects.

ON Semiconductor’s Mike Sandyck checks out how low-power LEDs and intelligent drivers could make visible light data communication plausible and some of the potential applications.

And don’t miss the blogs featured in the latest Manufacturing, Packaging & Materials newsletter:

Executive editor Mark LaPedus finds some surprises in a SEMI analyst fab forecast.

Coventor’s Jeonghoon (James) Kim advocates a well-defined process library that allows known good processes to be quickly tested to assist in defect identification and correction.

Amkor’s Yoshio Matsuda explains how various optimizations to the Exposed Pad TQFP package were required to achieve automotive grade.

Calibra’s Jan Willis looks at the tradeoffs involved in defining a new curvilinear data format to reduce file sizes.

SEMI’s Sungho Yoon urges wafer suppliers to boost capacity as market demand and average selling prices continue to improve.

Fraunhofer’s Christoph Sohrmann explains why a model-driven development approach is so important for speeding up the development process.