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Using Virtual Process Libraries To Improve Semiconductor Manufacturing

A well-defined process library allows known good processes to be quickly tested to assist in defect identification and correction.

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People think that semiconductor process simulation libraries should be developed using a perfect theoretical background that is strongly supported by empirical data. This might be true in academic research, where researchers are trying to develop a systematic approach to understanding a process mechanism. However, it is definitely not true in production fabs, where engineers need to quickly assess test wafers and want to avoid wasting production time and cost. It is more important in the fab to have a large and accurate behavioral process library then a theoretically perfect one.

Virtual process library readiness

Once engineers have established a virtual process library that matches the behavior of actual processes, these virtual libraries don’t need maintenance or regular repeatability checks. Users can arrange processes in their desired order during simulation or mix processes to support a new process integration scheme. In certain cases, such as when a process defect solution is urgently required, the readiness of a process library can be more important than any other modeling capability. A well-defined process library allows known good processes to be quickly tested to assist in defect identification and correction.


Fig. 1: Example of a process library which is categorized by process and equipment.

Process module optimization and technology pathfinding

We will now demonstrate the use of a virtual process library to assist in process module optimization and technology pathfinding. Figure 2 displays the simulation results of three different types of etch processes contained in a SEMulator3D process library. Each of the etch processes was assigned a different bias to simulate variation in etch process directionality. The etch process was followed by four different types of depositions, to assess gap-fill performance for each etch condition.


Fig. 2: Simulation results displaying three different etch processes followed by four different deposition processes.

The simulation results demonstrate that Deposition Process #1 provides the best gap-fill performance for each incoming structure, if an intermediate treatment is not available. If deposition treatment is not possible, Etch Process #2 combined with Deposition Process #2 assures better connectivity at the via. Deposition Process #3 displays the worst performance of all deposition processes, as it leaves thin metal layers inside the via which may cause future reliability problems. Each of the three deposition processes has potential for failure if the incoming etched structure has an overhang at the top of the structure entrance. Consequently, we have modeled an intermediate treatment combined with one of our deposition processes, to decrease the deposition rate at the top of structure. As we can see on the right-hand side of figure 2, the deposition process combined with an intermediate treatment showed the best gap-fill performance and more finely tuned results.

Conclusion

Using a pre-built virtual process library, process assumptions can be tested quite rapidly. Surprisingly, the simulation results in this study were acquired in less than 5 minutes. To complete these 12 tests, we only needed to mix and match the required process steps from our virtual process library. If a user has a large and varied process library that is calibrated with reliable reference data, the results will be predictive and accurately reflect actual process results. Using a virtual process library, full factorial process experiments can also be simulated with very little effort, saving both expensive tool time and wafers. The only thing required to achieve these valuable results is the availability of a well-calibrated virtual process library. Once a process library is prepared, it can be used to optimize the best process steps for a specific module, without the time and expense of wafer-based testing.



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