Blog Review: Mar. 13

Address translation in PCIe; 1.6T Ethernet; algorithm-specific NPUs; battery drain analysis.


Cadence’s Geeta Arora explains the Address Translation Service in PCIe 6.0, which allows an I/O device to perform its own virtual to physical address translations without relying on the host’s CPU to reduce latency and improve overall system performance.

Synopsys’ John Swanson, Jon Ames, Priyank Shukla, and Varun Agrawal highlight the upcoming 1.6T iteration of the Ethernet standard and the data connectivity infrastructure needed to support the increased speed.

Siemens’ Spencer Acain suggests that high-level synthesis can enable rapid creation of algorithm-specific neural processing units for edge AI applications.

Arm’s Francisco Socal introduces the expansion of AMBA to the chiplet market with the CHI C2C specification, which leverages the existing single chip CHI protocol and defines how it is packetized, which enables it to be transported chiplet-to-chiplet.

Keysight’s Andrew Herrera finds that battery drain analysis is crucial when designing IoT devices and consumer electronics to measure battery consumption in different operation modes, analyze usage by various subsystems, assess the impact of environmental factors, and identify the components and circuits with high power consumption.

Ansys’ Benoit Chassaigne checks out ways that companies are looking to make product development practices more sustainable, including through simulation and use of digital twins.

The ESD Alliance’s Bob Smith chats with Dieter Therssen of Sigasi about the tenacity of Moore’s Law, RTL design complexity, and the importance of writing good test benches.

Plus, check out the blogs featured in the latest Automotive, Security & Pervasive Computing and Test, Measurement & Analytics newsletters:

Siemens EDA’s Ann Keffer, Arun Gogineni, and James Kim share the details of a new functional safety methodology used in an SoC-level automotive test case.

Synopsys’ William Ruby argues that auto IC designers must adopt many of the power reduction techniques used in the mobile space, such as power domain shutoff, voltage and frequency scaling, and effective clock and data gating.

Cycuity’s Jason Oberg explains how understanding the characteristics of transient execution vulnerabilities helps prevent future ones.

Infineon’s Andreas Schumacher suggests a “Semiconductor Tree” offers a better framework for discussing the different branches of the chip industry than focusing on feature size.

Renesas’ Shingo Kojima digs into vision AI models and how the latest accelerators make it possible to immediately process the results of image recognition and AI judgment.

Cadence’s Steve Brown shows how digital twins can help design more energy-efficient transportation and turbomachinery equipment to meet current environmental challenges.

Flex Logix’s Jayson Bethurem outlines why ICs need to be adaptable when exponential amounts of data is coming from a multitude of sources and formats.

Rambus’ Bart Stevens shows how to reduce the potential hardware attack surface as increasingly powerful devices process more data in more places.

Onto Innovation’s Nick Keller details a non-destructive solution for measuring repeating metals in a multi-layer stack.

Synopsys’ Jyotika Athavale digs into why reliability, availability, and serviceability (RAS) expectations are growing and targets are continuing to get more stringent.

NI’s Alejandro Escobar Calderon explains how a non-terrestrial network structure goes beyond conventional limits, utilizing satellite and aerial platforms that can provide seamless connectivity worldwide.

Nordson’s Chris Rand shows how various inspection technologies complement each other, such as the use of both acoustic and X-ray inspection, or 2D X-ray imaging and 3D inspection.

Bruker Optics’ Inga Koehler notes that choosing the correct laser wavelength for a Raman spectroscopy application depends on factors like resonance, fluorescence, and sample absorption.

proteanTecs’ Noam Brousard delves into the intricacies of power consumption by exploring the economics of CPUs, GPUs, and AI accelerators.

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