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Blog Review: Mar. 6

From SDRAM to DDR5; what 112Gbps SerDes takes; building in-memory compute.

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Synopsys’ Snigdha Dua traces the evolution of memory from SDRAM to DDR5 and the techniques that provide each generation’s speed increase.

Cadence’s Paul McLellan digs into the challenges of 112Gbps SerDes, including what makes PAM4 signaling different from NRZ and what goes into equalization and modeling.

Mentor’s Rich Edelman provides a quick tutorial on how to set up a custom UVM report server, in this case, one that produces messages which have column-ized fields.

Applied Materials’ David Thompson explains what’s driven the push for research to develop in-memory compute architectures and build systems that approximate synapses and neurons.

Arm’s Ilias Vougioukas argues that hardware mitigation techniques should be the preferred option for dealing with side-channel attacks while balancing performance with security.

In a video, VLSI Research’s Dan Hutcheson chats with Mark Bohr of Intel about what caused the end of Dennard Scaling and where the industry looked next.

A Rambus writer argues that GDDR6, HBM, and memory buffers are critical technologies for IoT, 5G, and AI, with interfaces between both high performance processors as well as between processors and external memories.

SEMI’s Serena Brischetto chats with Loïc Lietar, CEO and co-founder of GreenWaves Technologies, about how open source benefits semiconductor startups and the role of public funding in providing initial capital.

Plus, check out the blogs featured in last week’s System-Level Design newsletter:

Editor In Chief Ed Sperling argues that even before the industry begins shifting to a data-driven approach, ground rules need to be established.

Technology Editor Brian Bailey questions whether antitrust law needs updating for the data age.

Mentor’s Ahmed Ramadan and Greg Curtis warn that because devices need to operate reliably for longer than ever before, aging simulation is vital.

Synopsys’ Tom De Schutter examines the benefits of starting early on the complex firmware development required by next-generation SSDs.

Cadence’s Frank Schirrmeister provides 5 takeaways from Embedded World 2019, from safety and security to ecosystems.

OneSpin’s Sven Beyer explains why as RISC-V offerings expand, it’s vital to make sure they conform to the ISA specification.

Silexica’s Andrew Caples explains that embedded software development is no longer a one-dimensional problem and tools need to adapt.

UltraSoC’s Andy Gothard looks at how RISC-V’s open-source ISA ecosystem is taking big steps forward with the latest foundation member announcements.

eSilicon’s Mike Gianfagna describes presenting a paper at ISSCC.



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