Evolution of test; data server memory; barrier transactions; state of IoT; DDoS on the rise.
In a video, Mentor’s Wally Rhines discusses the evolution of test methodologies and the forces that will change test priorities.
Cadence’s Priya Balasubramanian explores memory trends in data servers driven by the Internet’s massive need for bandwidth.
Synopsys’ Aadil Trikha presents a primer on the types of AMBA ACE barrier transactions.
ARM’s Simon Segars examines the state of IoT deployment and where challenges lie.
Rambus’ Aharon Etengoff looks at why large DDoS attacks are on the rise, and what can be done about it.
NI’s James Kimery points out three things to watch for at the Mobile World Conference.
GlobalFoundries’ Nitin Kulkarni looks back at CES and the show’s five big trends, from drones to VR.
Cadence’s Paul McLellan considers target impedance in power delivery networks.
Mentor’s Tom Fitzpatrick looks at the latest developments of the IEEE 1800.2 UVM standard.
And if you missed last week’s System-Level Design newsletter, check out these featured blogs:
Editor In Chief Ed Sperling argues that the acceleration of artificial intelligence will have big social and business impacts that need to be addressed.
Technology Editor Brian Bailey proposes a way to improve the EDA industry’s top conference for functional verification.
Aldec’s Sergei Zaychenko points to a simple but effective way to find bugs in ASIC and FPGA designs.
Mentor Graphics’ Sudhakar Jilla and Arvind Narayanan examine the role of new physical synthesis technologies for mitigating IP development risks.
Synopsys’ Pat Sheridan looks at how to close the loop with key performance indicators.
eSilicon’s Mike Gianfagna contends that open, transparent collaboration among companies is vital for a successful project.
Cadence’s Frank Schirrmeister finds some interesting application-specific changes as verification expands to cover more aspects of system development.
OneSpin Solutions’ Dave Kelf prepares for an insightful and educational four days at DVCon.
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