Blog Review: March 15

Siemens EDA’s Dan Yu finds that high-quality, well-connected mass data are crucial to the success of applying machine learning to verification and recommends teams pivot to a data-centric workflow.

Synopsys’ Shankar Krishnamoorthy suggests that deploying AI-driven chip design and verification can free teams from iterative work, letting them focus instead on product differentiation and PPA enhancements.

In a video, Cadence’s Neha Joshi explains how to do cloning and rewiring for inserted clock gates during wrapper cell insertion.

Ansys’ Kim Woodham and Laura Carter note that for cars to reach high levels of autonomy, they need to combine advanced sensor technology, precise determinization of vehicle location, up-to-date mapping information, local perception of other vehicles and pedestrians, and planning and decision making.

SEMI’s Ashley Huang looks at the rising profile of compound semiconductors as power supply design engineers try to find new ways to pack more power into less space while increasing device performance and reducing costs.

Renesas’ Graeme Clark explains the Asynchronous General Purpose Timer, a down counter that can be used for pulse output, external pulse width or period measurement, and counting external events in low power designs.

Arm’s Peterson Quadros considers the functional safety certification requirements for software tools used in automotive development.

Memory expert Ron Neale explores ULTRARAM, a triple barrier resonant tunnelling (TBRT) non-volatile memory being developed by Lancaster University, and suggests it could take peripheral memory technology in a radical new direction away from silicon and towards new compound material based integrated circuits.

Nvidia’s Rick Merritt explains how confidential computing enables processing data in a trusted execution environment, often inside a remote edge or public cloud server, and proving that no one viewed or altered the work.

Lithography expert Chris Mack shares more highlights from the SPIE Advanced Lithography and Patterning Symposium, including the first commercial projection lithography tool.

And don’t miss the blogs featured in the latest Low Power-High Performance newsletter:

Rambus’ Lou Ternullo looks at sharing memory resources across CPUs and accelerators.

Synopsys’ Jerry Lotto advises finding the speed sweet spot to keep the price point of edge deployments manageable.

Cadence’s Paul McLellan explores separating the power delivery network from signal wiring to leverage benefits ranging from reduced IR drop to chip area scaling.

Siemens’ Janet Attar digs into how a little timing sacrifice can reclaim power metrics.

Arm’s Masoud Koleini proposes tuning parameters to achieve the required performance while optimally using available resources.

Ansys’ Graziella Alves shows how IIoT and operational data enable simulation on a much larger scale.

Quadric.io’s Jon Bunting warns that inference-focused benchmarks can distract SoC designers from optimizing performance for end-to-end AI applications.