Blog Review: March 4

Gate-level simulation required?; parameterized interfaces & testbenches; 7nm lithography; wind & wave; ARM development resources; LSS possibilities; cracked screens begone; PCIe, PHY, power; appraising Apple autos; engineering love.


Is gate-level simulation still necessary? Mentor’s Gordon Allan asserts it is, and gives a list of reasons why the pain is worth the peace of mind.

Synopsys’ Aron Pratt concludes his series on parameterization strategies with a process that allows the testbench to make use of parameterized interfaces without imposing limits on VIP access.

Should you use EUV or quadruple patterning for 7nm ICs? In a talk covered by Cadence’s Richard Goering, IBM lithography expert Lars Liebmann outlines a methodology that may provide some guidance.

Ansys’ Justin Nescott collects the week’s top tech tidbits. You’ve probably never seen a windmill like the one the Dutch want to build. But if it doesn’t pan out, just look to your heart – it was the design inspiration for a new wave power buoy.

ARM’s Tom Stevens gathered up all the technical resources scattered across the ARM Community, resulting in a great first stop for software engineers and developers.

How many uses are there for lensless smart sensors? Rambus’ Aharon Etengoff listens in on a MWC workshop filled with potential applications.

Applied Materials’ Max McDaniel is on a quest to make broken smartphone screens (and clunky cases) a thing of the past.

PIPE power problems? Synopsys’ Saurabh Shrivastava throws some light on the different power states of Intel’s PHY Interface for PCI Express.

Cadence’s Axel Scherer looks at the complexities of modern product development and whether Apple’s past shows the adaptability necessary to dive into the auto market.

In celebration of National Engineer’s Week, Mentor’s Robin Bornoff shares his story of a picture, a paper, and how they led him to love mechanical engineering.

And in case you missed last week’s System-Level Design newsletter, here are some noteworthy blogs:

Editor in Chief Ed Sperling contends that chips are becoming more reliable in critical environments, but the initial design is aging too quickly.

Technology Editor Brian Bailey digs into the IEEE’s updated bylaws regarding licensing of standard essential patents and finds objectors who are ready to abandon the standards body.

Arteris’ Kurt Shuler examines specialized teams that are finding new ways to stitch individual efforts into the SoC fabric.

Mentor Graphics’ Jon McDonald questions what level of accuracy is required to ensure the platforms and models being used accurately represent the characteristics being analyzed.

Open-Silicon’s Dhananjay Wagh takes a look at how to break through the memory bandwidth wall.

Cadence’s Frank Schirrmeister observes that power is limited, and the best way to deal with it is by using early and accurate power analysis.

Synopsys’ Tom De Schutter opens a new chapter in how virtual prototypes were used for a multi-function printer SoC.

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