Blog Review: May 8

Synopsys’ Manuel Mota and Michael Posner look to UCIe as a complete stack for the die-to-die interconnect in multi-die chip designs, finding it can help maintain latency while reducing power and enhancing performance along with providing assurance of interoperability.

Cadence’s Durlov Khan highlights the Octal SPI interface for serial NAND flash, which enables 8-bit wide high bandwidth synchronous data transfers at manageable clock speeds.

Siemens’ Bill Ji finds that understanding the PCB assembly process is important to initial library creation and forming a design for manufacturing strategy early in the design process.

Arm’s Andrew Jones points to several key areas that have significant security implications for software-defined vehicles: digital cockpit and in-vehicle infotainment, ADAS and autonomous driving, and microcontrollers and zonal architectures.

Keysight’s Hwee Yng explores the evolution of in-vehicle networking as automotive Ethernet and SerDes approach 100 gigabits per second bandwidths and manufacturers look to add wireless technologies.

Infineon’s Alfredo Perez notes how LE Coded PHYs and Advertising Coding Selection work together to improve the range of Bluetooth.

Ansys’ Thierry Marchal checks out an effort to develop and validate an in silico model of the digestive system, with specific attention to the manner in which the stomach mixes and separates different types of solids and liquids.

SEMI’s Margaret Kindling chats with Brittney Graff of Brooks Instrument and Mayrita Arrandale of Applied Materials about supporting a diverse workforce and inspiring female students to pursue a career in the semiconductor industry.

For a change of pace, check out a recent video:

Right-sizing chiplets and other components based on real workloads as part of Adapting To Evolving IC Requirements.

Sensor Fusion Challenges In Automotive and why a single, centralized architecture is so critical for sensors.

How analytics can improve yield in high-volume manufacturing of panels with Overlay Optimization In Advanced IC Substrates.

Secure Movement Of Data In Test and why heterogeneous integration changes how data is used in manufacturing.

The benefits and challenges in heterogeneous integration include Challenges With Chiplets And Power Delivery.

Challenges In RISC-V Verification include how to debug a multi-core chip and ensure it will be cache coherent and secure.

Cache Coherency In Heterogeneous Systems and why maintaining flexibility in coherency is essential.

As features and functions increase, so do the complexity and costs of developing chips, leading to Rethinking Chip Economics.

The Cost And Quality Of Chiplets and why adaptive test is becoming necessary in heterogeneous designs.

Why automakers are shifting their emphasis from custom hardware to differentiating in software with more Changes And Challenges In Auto MCUs.

Modifying the source code allows for democratization of design, but it adds some hurdles for design teams and poses Integration Challenges For RISC-V Designs.

New Issues In Power Semiconductors include higher voltage and heterogeneous integration in advanced packages.

Yield Tracking In RDL, identifying defects in panel-level packages, and why that’s needed for generative AI in data centers.

How To Stop Row Hammer Attacks and why they have become such a significant security issue.

What’s Changing In DRAM as different memories are being mixed in the same design to deal with an explosion in data.

New approaches to improving utilization while reducing guard-banding as part of Reducing Power In Data Centers.

Using Deep Data For Improved Reliability Testing and to determine how close an individual device is to failure.