Blog Review: Nov. 8

Siemens’ Todd Westerhoff takes a look at the three stages of power integrity analysis for PCBs, challenges to board-level signal integrity, and best practices for getting the most accurate estimate of design performance.

Synopsys’ William Ruby provides a brief overview of the evolution of low-power design techniques and finds opportunities to reduce power and to make chip designs more energy efficient at higher levels of abstraction.

Cadence’s P Saisrinivas introduces the basics of interposers and how they are used in advanced packaging.

Arm’s Nicolas Devillard explains the Pointer Authentication and Branch Target Identification security techniques and how they can be used to mitigate certain classes of security vulnerabilities, including memory safety violations and memory corruption, without touching a single line of code in the software base.

Ansys’ Ashok Alagappan checks out how the design failure mode and effect analysis, or DFMEA, process helps teams understand potential failure modes early in product development and mitigate the impacts before costly failures show up in production, qualification testing, or the field.

Codasip’s Roddy Urquhart highlights the risks of memory safety vulnerabilities such as buffer overflows or over-reads and the increase in cyberattacks on firmware and embedded systems.

SEMI’s Serena Brischetto chats with industry experts about what’s driving the adoption of atomic layer deposition (ALD), solutions for addressing the interfacial layer and surface passivation challenges, and the benefits for GaN power devices.

Infineon’s Skip Ashton finds that the latest version of the Matter specification marks the beginning of the defragmentation of the smart home industry and increasing support for a consistent and reliable unified standard.

Keysight’s Alan Wadsworth checks out normal, power supply, high capacitance, and laser diode operation modes in source/monitor units (SMUs) and gives examples for when they would be used.

AWS’ Denis Sukachev, Chawina De-Eknamkul, and Beibei Zeng introduce a temperature-resistant packaging technique for optical devices used in quantum networking that can withstand multiple cycles of cooling from room temperature to cryogenic temperatures and back.

Plus, check out the blogs featured in the latest Automotive, Security & Pervasive Computing and Test, Measurement & Analytics newsletters:

Rambus’ Bart Stevens examines key elements and actions for preserving data integrity.

Siemens EDA’s Mohammed Abdelwahid lays out a multi-layer security approach using DFT and embedded analytics.

Cadence’s Kunal Chhabriya explains how to test the transmitter and interconnect to assess whether their voltage and timing meet the specification.

Renesas’ Balaji Kanigicherla warns that a widening performance mismatch threatens to compromise server performance.

Flex Logix’s Geoff Tate looks at pipelining key portions of the scan circuitry to increase scan speed.

Infineon’s Ashwin Kumar explains why MPUs (memory protection units) are so critical and how to implement them.

Onto Innovation’s Vamsi Velidandla explains how to measure more data points on a wafer without impacting overall fab throughput.

Synopsys’ Ramsay Allen examines the ideal characteristics of a DFT connectivity checking solution, identifying the root cause of failures while minimizing false violations and noise.

NI’s Alejandro Escobar Calderon digs into the importance of FiRa certification for test vendors.

Teradyne’s Regan Mills looks at the systems and guardrails needed to identify inaccurate AI/ML results.

Bruker’s Xia Stammer provides a brief history of quantum dots and their various applications.