Blog Review: Oct. 2

Finite element analysis; false claims; HPC utilization.


In a video, Cadence’s Tom Hackett explains finite element analysis by looking at a simple model of a bridge and showing why FEA techniques are required for analysis of real-world structures.

Synopsys’ Taylor Armerding examines why the 156-year-old False Claims Act has new relevance when companies are accused of failing to meet cybersecurity standards.

Mentor’s Colin Walls demystifies memory management units and when you should consider using them.

Arm’s Alex Rico digs into the problem of underutilization of resources in high-performance computing and how tasking can help improve load balancing and increase system utilization with better locality.

ANSYS’ Paolo Colombo considers how close we are to fully autonomous aircraft, the innovations that have made the current level of self-flying planes possible, and the next steps toward greater autonomy.

A Rambus writer examines a new exploit targeting Data-Direct I/O (DDIO), found in recent generations of Intel server processors, which enables an attacker to build a covert channel between a network client and a sandboxed server process and extract network timing-based sensitive information.

SEMI’s Serena Brischetto talks with Christoph Kutter of Fraunhofer EMFT about flexible hybrid electronics, innovative integration approaches, and the market opportunities that lie ahead.

Nvidia’s Isha Salian checks out a project to use AI to help identify and treat banana diseases.

Silicon Labs’ Jackie Padgett chats with David Simpson of Enseo on how to provide hospitality and housekeeping employees with an IoT safety alert device while still protecting their privacy.

And don’t miss the blogs featured in the latest System-Level Design newsletter:

Editor in Chief Ed Sperling examines the impact of 1 trillion connected devices.

Technology Editor Brian Bailey questions who will win the battle for AI architectures.

OneSpin’s Dominik Strasse explains why C++/SystemC design expectations need to be set properly.

Cadence’s Frank Schirrmeister finds progress in programming language concurrency 15 years after the multicore crisis.

Mentor’s Nermeen Hossam and John Ferguson contend that specific verification strategies can enable full-chip layout exploration and physical verification even if many components are immature.

Synopsys’ Ruben Molina observes a growing use of high-performance computing for non-research applications.

eSilicon’s Mike Gianfagna files dispatches from the AI Hardware Summit and ECOC 2019.

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