Blog Review: Oct. 9

EUV and 450mm, consolidation, aliens, unknowns, VIP, embedded processors, EDA’s evolution.

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By Ed Sperling
Mentor’s Simon Favre raises an interesting question: Why are 450mm wafers and EUV lithography related? The answer may surprise you.

In his second broadcast, Cadence’s Brian Fuller interviews Gary Smith about where EDA will grow, why industry consolidation is a myth and why there is a dearth of reliable information about the electronics industry.

Synopsys’ Mick Posner combats aliens in his RTL. And you thought this was all a game.

Real Intent’s Graham Bell drills into SoC signoff analysis and the proliferation of X’s, or unknowns. There’s a good video interview of what can go wrong as complication increases along with time-to-market pressures.

Semico Research’s Jim Feldhan notes that increasing design cycle times coupled with shorter product life cycles are forcing some changes in the SoC world, with big implications for IP.

Independent blogger Gaurav Jalan has developed a recipe for verification IP, and what determines whether you make the stuff or order takeout.

Mentor’s Harry Foster has some stats about the number of processors in SoC designs and its impact on verification. There’s a link to a story about ST’s experience in simulation and verification, too. Plan on staying awhile.

Cadence’s Richard Goering looks at TSMC’s checklist for 16nm finFET design, ranging from RC extraction to EM, static timing analysis and ESD. That’s a lot of checks, and some of them need to be marked in pencil.

Synopsys’ Eric Huang is back with a look at media-agnostic USB. He’s also looking for politically correct jokes about USB. The lines are buzzing.

ARM’s Joe Bungo looks at an academic conference about embedded systems R&D. Apple came to the conclusion in the 1980s that to win a market you have to build a following. It seems to have worked.

Mentor’s Colin Walls looks at what’s transpired in the span of a month, making predictions about the next big thing rather difficult to define. This is like a new version of constrained random logic.

Cadence’s Jason Andrews spots some trends in using software for system verification. Make sure to check out the recent job listing.